LMK04832 Datasheet, PDF (1/8 Pages) Texas Instruments – LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs

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LMK04832 Ultra Low-Noise JESD204B Compliant
Clock Jitter Cleaner With Dual Loop PLLs
LMK04832
SNAS752 – AUGUST 2017
1 Features
•1 Maximum Clock Output Frequency: 3250 MHz
• Multi-Mode: Dual PLL, Single PLL, and Clock
Distribution
• Ultra-Low Noise, at 3200 MHz:
– 47 fs RMS Jitter (12 kHz to 20 MHz)
– 50 fs RMS Jitter (100 Hz to 100 MHz)
– –158 dBc/Hz Noise Floor
• PLL2
– PLL FOM of –230 dBc/Hz
– PLL 1/f of –126 dBc/Hz
– Phase Detector Rate up to 320 MHz
– Two Integrated VCOs: 2495 to 2705 MHz
and 2945 to 3205 MHz
• Up to 14 Differential Device Clocks
– CML, LVPECL, LCPECL, HSDS, LVDS, and
2xLVCMOS Programmable Outputs
• Up to 1 Buffered VCXO/XO Output
– LVPECL, LVDS, 2xLVCMOS Programmable
• Capable of 3.13-MHz Device Clock from 3.2 GHz
• Capable of 391-kHz SYSREF from 3.2 GHz
• 25-ps Step Analog Delay for SYSREF Clocks
• Digital Delay and Dynamic Digital Delay for
Device Clock and SYSREF
• Holdover Mode with PLL1
• 0-Delay with PLL1 or PLL2
• +125°C Junction Temperature
• Supports 105°C PCB Temperature (Measured at
Thermal Pad)
2 Applications
• Test and Measurement
• RADAR
• Microwave Backhaul
• Data Converter Clocking
3 Description
The LMK04832 is the industry's highest performance
clock conditioner with JEDEC JESD204B support and
is also pin compatible with the LMK0482x family of
devices.
The 14 clock outputs from PLL2 can be configured to
drive seven JESD204B converters or other logic
devices using device and SYSREF clocks. SYSREF
can be provided using both DC and AC coupling. Not
limited to JESD204B applications, each of the 14
outputs can be individually configured as high
performance outputs for traditional clocking systems.
The LMK04832 can be configured for operation in
dual PLL, single PLL, or clock distribution modes with
or without SYSREF generation or reclocking. PLL2
may operate with either internal or external VCO.
The high performance combined with features like the
ability to trade off between power and performance,
dual VCOs, dynamic digital delay, and holdover make
the LMK04832 ideal for providing flexible high
performance clocking trees.
Device Information⁽¹⁾
PART NUMBER
DESCRIPTION BODY SIZE (NOM)
LMK04832NKDT
LMK04832NKDR
WQFN (64)
9 mm x 9 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) T = Tape; R = Reel
Simplified Schematic
Recovered
³GLUW\´ FORFN RU
clean clock
VCXO
or XO
CLKin0
Backup
Reference
Clock
CLKin1
ADC
CLKout0 &
CLKout2
CLKout1 &
CLKout3
CLKout10
CLKout11
LMK04832
OSCout
CLKout8
CLKout9
CLKout4 &
CLKout6
CLKout5 &
CLKout7
CLKout12,
CLKout13
LMX2594
PLL+VCO
FPGA
DDAACC
0XOWLSOH ³FOHDQ´
clocks at different
frequencies
Serializer/
Deserializer
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.