LM4312 Datasheet, PDF (1/25 Pages) Texas Instruments – LM4312 Mobile Pixel Link Two (MPL-2), RGB Display Differential Interface Serializer with Optional Dithering and Look Up Table

LM4312
www.ti.com
SNLS265A – MAY 2008 – REVISED MAY 2013
LM4312 Mobile Pixel Link Two (MPL-2), RGB Display Differential Interface Serializer with
Optional Dithering and Look Up Table
Check for Samples: LM4312
FEATURES
1
•2 RGB Display Interface to >640 x 480 (VGA)
Resolution
• 24 or 18-bit RGB Transport
• 24–to–18-bit RGB Dithering Option
• Look Up Table Option for Independent Color
Correction Option
• Robust MPL-2 Differential SLVS Interface
• SPI Interface for Configuration / Control and
LUT Options
• Low Power Consumption & SLEEP State
• Auto Power Down on STOP PCLK
• Automatically Generates Frame Sequence Bits
for Resync upon Data or Clock Error
• Odd Parity Generation
SYSTEM BENEFITS
• Dithered Data Reduction
• Independent RGB Color Correction
• 24-bit Color Input
• Small Robust Interface
• Low Power & Low EMI
DESCRIPTION
The LM4312 is a MPL-2 Serializer (SER) that accepts
a 24- or 18-RGB interface and serializes this wide
bus to 3 differential signals. The optional Dithering
feature can reduce 24-bit RGB to 18-bit RGB. The
optional Look Up Table (Three X 256 X 8 bit RAM) is
provided for independent color correction. 18-bit
Bufferless displays from QVGA (320 x 240) up to
>VGA (640 x 480) pixels are supported.
The interconnect is reduced from 28 LVCMOS
signals (RGB888+V+H+DE+PCLK) to only 3 active
differential signals (DD0P/M, DCP/M, DD1P/M) with
the LM4312 Serializer and companion LM4310
Deserializer easing flex interconnect design, size
constraints and cost.
The LM4312 SER resides by the application, graphics
or baseband processor and translates the wide
parallel video bus from LVCMOS levels to serial
MPL-2 levels for transmission over a flex cable and
PCB traces to the DES located in the display module.
When in Power_Down, the SER is put to sleep and
draws less than 10μA. The SER can be powered
down by stopping the PCLK or by asserting its PD*
input pin.
The LM4312 implements the physical layer of the
MPL-2 Interface and features robust common-mode
noise rejection.
Typical Application Diagram - Bridge Chips - 24-bit to 18-bit RGB
Apps
Processor
---
Graphics
Processor
---
Baseband
Processor
R[7:0]
G[7:0]
B[7:0]
VS
HS
DE
PCLK
SPI_CSX
SPI_SCL
SPI_DI
SPI_DO
PD*
LM4312 Serializer
D
i
t
P
h
2
e
S
r
PLL
S
PCLK
P
Three
I
256 x 8
LUTs
Configuration
LM4310 Deserializer
DD0
DC
DD1
S
2
P
Config.
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
PCLK
PE
PD*
RDS
Mode24
RGB Display
VGA
18-Bit Color Depth
[Supply, all Configuration pins, and bypass caps. and grounding not shown]
1
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