ISO7221C-HT Datasheet, PDF (1/16 Pages) Texas Instruments – DUAL DIGITAL ISOLATOR

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DUAL DIGITAL ISOLATOR
Check for Samples: ISO7221C-HT
ISO7221C-HT
SLLSE78 – APRIL 2011
FEATURES
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• 1-, 5- and 25-Mbps Signaling Rate Options
– Low Channel-to-Channel Output Skew;
1 ns max
– Low Pulse-Width Distortion (PWD);
1 ns max
– Low Jitter Content; 1 ns Typ at 150 Mbps
• 4000-V_peak Isolation, 560 V_peak V_IORM
– UL 1577 Approved
– 50-kV/μs Typical Transient Immunity
• Operates with 3.3-V or 5-V Supplies
• 4-kV ESD Protection
• High Electromagnetic Immunity
APPLICATIONS
• Down-Hole Drilling
• High Temperature Environments
SUPPORTS EXTREME TEMPERATURE
APPLICATIONS
• Controlled Baseline
• One Assembly/Test Site
• One Fabrication Site
• Available in Extreme (–55°C/175°C)
Temperature Range⁽¹⁾⁽²⁾
• Extended Product Life Cycle
• Extended Product-Change Notification
• Product Traceability
• Texas Instruments high temperature products
utilize highly optimized silicon (die) solutions
with design and process enhancements to
maximize performance over extended
temperatures.
ISO7221C
V_CC1 1
OUTA ²
INB ³
GND1 ⁴
8 _VCC2
7 _INA
6 OUTB
5 GND2
(1) Custom temperature ranges available.
(2) Device is qualified to ensure reliable operation for 1000 hours
at maximum rated temperature. This includes, but is not
limited to temperature bake, temperature cycle, electro
migration, bond inter metallic life, and mold compound life.
Such qualification testing should not be viewed as justifying
use of this component beyond specified performance and
environmental limits.
DESCRIPTION
The ISO7221 is a dual-channel digital isolator. To facilitate PCB layout, the channels are oriented in the opposite
directions. This device has a logic input and output buffer separated by TI’s silicon-dioxide (SiO₂) isolation
barrier, providing galvanic isolation of up to 4000 V. Used in conjunction with isolated power supplies, this device
blocks high voltage, isolates grounds, and prevents noise currents on a data bus or other circuits from entering
the local ground and interfering with or damaging sensitive circuitry.
A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation
barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or
resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure
the proper dc level of the output. If this dc-refresh pulse is not received every 4 μs, the input is assumed to be
unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state.
The small capacitance and resulting time constant provide fast operation with signaling rates available from
0 Mbps (dc) to 150 Mbps.⁽³⁾ The A-, B- and C-option devices have TTL input thresholds and a noise filter at the
input that prevents transient pulses from being passed to the output of the device. The M-option devices have
CMOS V_CC/2 input thresholds and do not have the input noise-filter and the additional propagation delay.
(3) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated