DS90UH925AQ-Q1 Datasheet, PDF (1/56 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

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DS90UH925AQ-Q1
SNLS481 – JUNE 2014
DS90UH925AQ-Q1 720p 24-bit Color FPD-Link III Serializer with HDCP
1 Features
•1 Integrated HDCP Cipher Engine with On-chip Key
Storage
• Bidirectional Control Interface Channel Interface
with I2C Compatible Serial Control Bus
• Supports High Definition (720p) Digital Video
Format
• RGB888 + VS, HS, DE and I2S Audio Supported
• 5 – 85 MHz PCLK Supported
• Single 3.3 V Operation with 1.8 V or 3.3 V
Compatible LVCMOS I/O Interface
• AC-coupled STP Interconnect up to 10 meters
• Parallel LVCMOS Video Inputs
• DC-balanced & Scrambled Data with Embedded
Clock
• Supports HDCP Repeater Application
• Dedicated Interrupt Pin for Remote Interrupts
• Internal Pattern Generation
• Low Power Modes Minimize Power Dissipation
• Automotive Grade Product: AEC-Q100 Grade 2
Qualified
• >8 kV HBM and ISO 10605 ESD rating
• Backward Compatible Modes
2 Applications
• Automotive Touch Screen Display
• Automotive Display for Navigation
• Rear Seat Entertainment Systems
3 Description
The DS90UH925AQ serializer, in conjunction with the
DS90UH926Q deserializer, provides a solution for
secure distribution of content-protected digital video
within automotive entertainment systems. This
chipset translates a parallel RGB Video Interface into
a single pair high-speed serialized interface. The
digital video data is protected using the industry
standard HDCP copy protection scheme. The serial
bus scheme, FPD-Link III, supports video and audio
data transmission and full duplex control including
I2C communication over a single differential link.
Consolidation of video data and control over a single
differential pair reduces the interconnect size and
weight, while also eliminating skew issues and
simplifying system design.
The DS90UH925AQ serializer embeds the clock,
content protects the data payload, and level shifts the
signals to high-speed low voltage differential
signaling. Up to 24 RGB data bits are serialized along
with three video control signals and up to two I2S
data inputs.
EMI is minimized by the use of low voltage differential
signaling, data scrambling and randomization and
spread spectrum clocking compatibility.
The HDCP cipher engine is implemented in the
serializer and deserializer. HDCP keys are stored in
on-chip memory.
Remote interrupts from the downstream
DS90UH926Q deserializer are mirrored to a local
output pin.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS90UH925AQ-Q1 WQFN RHS (48) 7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
HOST
Graphics
Processor
VDDIO VDD33
(1.8V or 3.3V) (3.3V)
VDD33 VDDIO
(3.3V) (1.8V or 3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
PDB
3
I2S AUDIO _/
(STEREO)
SCL
SDA
IDx
DOUT+
DOUT-
DS90UH925AQ
Serializer
DAP
FPD-Link III
1 Pair /AC Coupled
0.1 2F
0.1 2F
100 ohm STP Cable
PDB
OSS_SEL
OEN
MODE_SEL
MODE_SEL
INTB
REM_INTB
INTB_IN
SCL
SDA
IDx
RIN+
RIN-
DS90UH926Q
Deserializer
DAP
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
RGB Display
720p
24-bit color depth
LOCK
PASS
3
/
I2S AUDIO
(STEREO)
MCLK
Typical Eye Diagram
Time (100 ps/DIV)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.