DS90LV018A_13 Datasheet, PDF (1/17 Pages) Texas Instruments – 3V LVDS Single CMOS Differential Line Receiver

DS90LV018A
www.ti.com
SNLS014D – JUNE 1998 – REVISED APRIL 2013
DS90LV018A 3V LVDS Single CMOS Differential Line Receiver
Check for Samples: DS90LV018A
FEATURES
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•2 >400 Mbps (200 MHz) Switching Rates
• 50 ps Differential Skew (Typical)
• 2.5 ns Maximum Propagation Delay
• 3.3V Power Supply Design
• Flow-Through Pinout
• Power Down High Impedance on LVDS Inputs
• Low Power Design (18mW @ 3.3V Static)
• Interoperable with Existing 5V LVDS Networks
• Accepts Small Swing (350 mV Typical)
Differential Signal Levels
• Supports Open, Short and Terminated Input
Fail-Safe
• Conforms to ANSI/TIA/EIA-644 Standard
• Industrial Temperature Operating Range
– (−40°C to +85°C)
• Available in SOIC Package
DESCRIPTION
The DS90LV018A is a single CMOS differential line
receiver designed for applications requiring ultra low
power dissipation, low noise and high data rates. The
device is designed to support data rates in excess of
400 Mbps (200 MHz) utilizing Low Voltage Differential
Signaling (LVDS) technology.
The DS90LV018A accepts low voltage (350 mV
typical) differential input signals and translates them
to 3V CMOS output levels. The receiver also
supports open, shorted and terminated (100Ω) input
fail-safe. The receiver output will be HIGH for all fail-
safe conditions. The DS90LV018A has a flow-through
design for easy PCB layout.
The DS90LV018A and companion LVDS line driver
provide a new alternative to high power PECL/ECL
devices for high speed point-to-point interface
applications.
Connection Diagram
Functional Diagram
Figure 1. SOIC
See Package Number D (R-PDSO-G8)
Truth Table
INPUTS
[R_IN+] − [R_IN−]
V_ID ≥ 0.1V
V_ID ≤ −0.1V
Full Fail-safe OPEN/SHORT or Terminated
OUTPUT
R_OUT
H
L
H
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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