DS25BR100_14 Datasheet, PDF (1/19 Pages) Texas Instruments – 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

DS25BR100
www.ti.com
SNLS217E – MARCH 2007 – REVISED MAY 2011
DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and
Receive Equalization
Check for Samples: DS25BR100
FEATURES
1
•2 DC - 3.125 Gbps
– Low Jitter
– High Noise Immunity
– Low Power Operation
• Receive equalization reduces ISI jitter due to
media loss
• Transmit pre-emphasis drives lossy
backplanes and cables
• On-chip 100Ω input and output termination:
– Minimizes insertion and return losses
– Reduces component count
– Minimizes board space
• DS25BR101 eliminates on-chip input
termination for added design flexibility
• 7 kV ESD on LVDS I/O pins protects adjoining
components
• Small 3 mm x 3 mm LLP-8 space saving
package
APPLICATIONS
• Clock and data buffering
• Metallic cable driving and equalization
• FR-4 equalization
DESCRIPTION
The DS25BR100 and DS25BR101 are single channel 3.125 Gbps LVDS buffers optimized for high-speed signal
transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. Fully differential
signal paths ensure exceptional signal integrity and noise immunity.
The DS25BR100 and DS25BR101 feature transmit pre-emphasis (PE) and receive equalization (EQ), making
them ideal for use as a repeater device. Other LVDS devices with similar IO characteristics include the following
products. The DS25BR120 features four levels of pre-emphasis for use as an optimized driver device, while the
DS25BR110 features four levels of equalization for use as an optimized receiver device. The DS25BR150 is a
buffer/repeater with the lowest power consumption and does not feature transmit pre-emphasis nor receive
equalization.
Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the
output levels are LVDS. A very small package footprint requires minimal space on the board while the flow-
through pinout allows easy board layout. On the DS25BR100 the differential input and output is internally
terminated with a 100Ω resistor to lower return losses, reduce component count and further minimize board
space. For added design flexibility the 100Ω input terminations on the DS25BR101 have been eliminated. This
elimination enables a designer to adjust the termination for custom interconnect topologies and layout.
1
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2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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