DS250DF810 Datasheet, PDF (1/12 Pages) Texas Instruments – 25 Gbps Multi-Rate 8-Channel Retimer

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DS250DF810
SNLS495A – SEPTEMBER 2015 – REVISED JANUARY 2016
DS250DF810 25 Gbps Multi-Rate 8-Channel Retimer
1 Features
•1 Octal-Channel Multi-Rate Retimer with Integrated
Signal Conditioning
• All Channels Lock Independently from 20.6 to
25.8 Gbps (Including Sub-Rates Like 10.3125
Gbps, 12.5 Gbps, and More)
• Ultra-Low Latency: <500 ps typical for 25.78125
Gbps data rate
• Single Power Supply, No Low-Jitter Reference
Clock Required, and Integrated AC Coupling
Capacitors to Reduce Board Routing Complexity
and BOM Cost
• Integrated 2×2 Cross Point
• Adaptive Continuous Time Linear Equalizer
(CTLE)
• Adaptive Decision Feedback Equalizer (DFE)
• Low-Jitter Transmitter with 3-Tap FIR Filter
• Combined Equalization Supporting 35+ dB
Channel Loss at 12.9 GHz
• Adjustable Transmit Amplitude: 205 mVppd to
1225 mVppd (typical)
• On-Chip Eye Opening Monitor (EOM), PRBS
Pattern Checker/Generator
• Small 8 mm × 13 mm BGA Package with Easy
Flow-Through Routing
• Unique Pinout Allows Routing High-Speed Signals
Underneath the Package
• Pin-Compatible Repeater Available
2 Applications
• Backplane/Mid-plane Reach Extension
• Jitter Cleaning for Front-Port Optical
• IEEE802.3bj 100GbE, Infiniband EDR, and OIF-
CEI-25G-LR/MR/SR/VSR Electrical Interfaces
• SFP28, QSFP28, CFP2/CFP4, CDFP
3 Description
The DS250DF810 is an eight-channel multi-rate
Retimer with integrated signal conditioning. It is used
to extend the reach and robustness of long, lossy,
crosstalk-impaired high-speed serial links while
achieving a bit error rate (BER) of 10^-15 or less.
Each channel of the DS250DF810 independently
locks to serial data rates in a continuous range from
20.6 Gbps to 25.8 Gbps or to any supported sub-rate
(÷2 and ÷4), including key data rates such as 10.3125
Gbps and 12.5 Gbps, which allows the DS250DF810
to support individual lane Forward Error Correction
(FEC) pass-through.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS250DF810
135-pin fcBGA (135) 8.0 mm × 13.0 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
RX0P
.
RX_.0N
.
.
.
.
RX7P
RX7N
VDD
SMBus
Slave mode ^{1 NŸ}
EN_SMB
TEST
25 MHz
SMBus Slave
mode
2.5V
1 F 0.1 F
(2x)
(4x)
CAL_CLK_IN
READ_EN_N
VDD
TX0P
.
TX_.0N
.
.
.
.
TX7P
TX7N
INT_N
SDA⁽¹⁾
SDC⁽¹⁾
ADDR0
ADDR1
CAL_CLK_OUT
ALL_DONE_N
GND
.
.
.
2.5V or
3.3V
To other open-
drain interrupt
pins
To system SMBus
Address straps
(pull-up, pull-
down, or float)
7R QH[W GHYLFH¶V
CAL_CLK_IN
Float for SMBus Slave
mode, or connect to next
GHYLFH¶V 5($'_EN_N for
SMBus Master mode
(1) SMBus signals need to be pulled up elsewhere in the system.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.