DS250DF210 Datasheet, PDF (1/12 Pages) Texas Instruments – 25-Gbps Multi-Rate 2-Channel Retimer

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DS250DF210
SNLS560 – FEBRUARY 2017
DS250DF210 25-Gbps Multi-Rate 2-Channel Retimer
1 Features
•1 Dual-Channel Multi-Rate Retimer With Integrated
Signal Conditioning
• All Channels Lock Independently From 20.6 to
25.8 Gbps (Including Sub-Rates Such as 10.3125
Gbps, 12.5 Gbps, and More)
• Ultra-Low Latency: <500 ps Typical for 25.78125-
Gbps Data Rate
• Single Power Supply, No Low-Jitter Reference
Clock Required, and Minimal Supply Decoupling
to Reduce Board Routing Complexity and BOM
Cost
• Adaptive Continuous Time Linear Equalizer
(CTLE)
• Adaptive Decision Feedback Equalizer (DFE)
• Integrated 2 x 2 Cross Point
• Low-Jitter Transmitter With 3-Tap FIR Filter
• Combined Equalization Supporting 35+ dB
Channel Loss at 12.9 GHz
• Adjustable Transmit Amplitude: 205 mVppd to
1225 mVppd (Typical)
• On-Chip Eye Opening Monitor (EOM), PRBS
Pattern Checker and Generator
• Small 6-mm × 6-mm BGA Package With Easy
Flow-Through Routing
2 Applications
• Jitter Cleaning for Front-Port Optical
• Active Cable Assemblies
• Backplane and Mid-Plane Reach Extension
• IEEE802.3bj 100GbE, Infiniband EDR, and OIF-
CEI-25G-LR/MR/SR/VSR Electrical Interfaces
• SFP28, QSFP28, CFP2/CFP4, CDFP
3 Description
The DS250DF210 device is a two-channel, multi-rate
retimer with integrated signal conditioning. It is used
to extend the reach and robustness of long, lossy,
crosstalk-impaired, high-speed serial links while
achieving a bit error rate (BER) of 10^-15 or less.
Each channel of the DS250DF210 independently
locks to serial data rates in a continuous range from
20.6 Gbps to 25.8 Gbps or to any supported sub-rate
(÷2 and ÷4), including key data rates such as 10.3125
Gbps and 12.5 Gbps, which allows the DS250DF210
to support individual lane Forward Error Correction
(FEC) pass-through.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS250DF210
ABM (101)
6.00 mm × 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
RX0P
RX0N
RX
CDR
TX
TX0P
TX0N
RX1P
RX1N
RX
CDR
TX
VDD
SMBus
Slave mode ^{1 NŸ}
EN_SMB
NC_TEST
TX1P
TX1N
INT_N
SDA⁽¹⁾
SDC⁽¹⁾
25 MHz
CAL_CLK_IN
ADDR0
ADDR1
CAL_CLK_OUT
SMBus Slave
mode
2.5V
1F
0.1 F
(2x)
(4x)
READ_EN_N
VDD
ALL_DONE_N
GND
2.5V or
3.3V
To other open-drain
interrupt pins
To system
SMBus
Address straps
(pull-up, pull-
down, or float)
7R QH[W GHYLFH¶V
CAL_CLK_IN
Float for SMBus Slave
mode, or connect to next
GHYLFH¶V 5($'_EN_N for
SMBus Master mode
(1) SMBus signals need to be pulled up elsewhere in the system.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.