DRA718 Datasheet, PDF (1/3 Pages) Texas Instruments – Automotive Applications Processors Technical Brief

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DRA718
SPRT719 – FEBRUARY 2016
DRA71x Automotive Applications Processors Technical Brief
1 Introduction
This technical brief introduces the features, subsystems, and architecture of the DRA71x "Jacinto 6 Entry"
family of infotainment processors.
The DRA71x is a low cost processor targeting BOM-optimized entry infotainment systems such as display
audio and is a software compatible derivative of the highly successful "Jacinto 6" and "Jacinto 6 Eco"
processor families.
1
1.1 Features
• The features include:
– Streaming video up to full high definition (Full-
HD) (1920×1080p, 60 fps) including enablement
for bring-your-own-device (BYOD) functionality
– 2-dimensional (2D) and 3-dimensional (3D)
graphics and composition
– Decode of digital radio standards including HD
Radio™, DAB, and DRM, as well as analog
AM/FM/RDS capability
– Advanced audio processing, noise suppression,
and speech enhancement capabilities
– Support for multiple concurrent displays (one
high-definition) and video input/camera
• The device is composed of the following
subsystems:
– ARM^® Cortex^®-A15 microprocessor unit (MPU)
– One digital signal processor (DSP) C66x
subsystem
– Image and video accelerator high-definition
(IVA-HD) subsystem
– Two ARM Cortex-M4 processing subsystems,
each including two ARM Cortex-M4
microprocessors
– Display subsystem (DSS)
– Video processing (VPE) subsystem
– Video input capture (VIP) subsystem
– 3D-graphics processing unit (GPU) subsystem,
including POWERVR™ SGX544-MPx single-
core subsystem
– 2D-graphics accelerator (BB2D) subsystem,
including Vivante™ GC320 core
– Three pulse-width modulation (PWM)
subsystem
– Real-time clock (RTC) subsystem
– Debug subsystem
• The device provides a rich set of connectivity
peripherals, including:
– One USB3.0 and one UBS2.0 subsystems
– PCI Express Gen2 subsystem
– 3-port Gigabit Ethernet Switch subsystem
• The device also integrates:
– On-chip memory
– External memory interfaces
– Memory management
– Level 3 (L3) and level 4 (L4) interconnects
– System peripherals
– Car, audio and media peripherals including
CAN, MOST MLB, and Ethernet AVB
– Radio accelerators
1.2 Applications
• Automotive Display Audio Systems
• Automotive Entry Navigation and Multimedia
Systems
• Automotive Digital Cluster Systems
1.3 Description
The DRA71x processor is offered in a 625-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can
be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package. Figure 1-
1 is the block diagram of the DRA71x processor.
The architecture is designed to deliver high-performance concurrencies for automotive applications in a
cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"),
DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors, including graphics,
voice, HMI, multimedia and smartphone projection mode capabilities.
The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCT PREVIEW Information. Product in design phase of
development. Subject to change or discontinuance without notice.