DM385 Datasheet, PDF (1/280 Pages) Texas Instruments – DM385 and DM388 DaVinci™ Digital Media Processor

DM385, DM388
www.ti.com
SPRS821D – MARCH 2013 – REVISED DECEMBER 2013
DM385 and DM388 DaVinci™ Digital Media Processor
Check for Samples: DM385, DM388
1 High-Performance System-on-Chip (SoC)
1.1 Features
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• High-Performance DaVinci Digital Media
Processors
• Programmable High-Definition Video Image
Coprocessing (HDVICP v2) Engine
– Up to 1000-MHz ARM® Cortex™-A8 RISC
Processor
– Up to 2000 ARM Cortex-A8 MIPS
– Encode, Decode, Transcode Operations
– H.264 BP/MP/HP, MPEG-2, VC-1, MPEG-4
SP/ASP, JPEG/MJPEG
• ARM Cortex-A8 Core
– ARMv7 Architecture
• In-Order, Dual-Issue, Superscalar
Processor Core
– Fourth-Generation Motion-Compensated
Noise Filter (DM388 Only)
• Media Controller
– Controls the HDVPSS, HDVICP2, and ISS
• NEON™ Multimedia Architecture
• Endianness
• Supports Integer and Floating Point
– ARM Instructions and Data – Little Endian
• Jazelle® RCT Execution Environment
• HD Video Processing Subsystem (HDVPSS)
• ARM Cortex-A8 Memory Architecture
– Two 165-MHz HD Video Capture Inputs
– 32KB of Instruction and Data Caches
– 256KB of L2 Cache with ECC
– 64KB of RAM, 48KB of Boot ROM
• 256KB of On-Chip Memory Controller (OCMC)
RAM
• Imaging Subsystem (ISS)
– Camera Sensor Connection
• Parallel Connection for Raw (up to 16-Bit)
and BT.656/BT.1120 (8- or 16-Bit)
• CSI2 Serial Connection
– Image Sensor Interface (ISIF) for Handling
Image and Video Data From the Camera
Sensor
– Image Pipe Interface (IPIPEIF) for Image and
Video Data Connection Between Camera
Sensor, ISIF, IPIPE, and DRAM
• One 16- or 24-Bit Input, Splittable Into
Dual 8-Bit SD Capture Ports
• One 8-, 16-, or 24-Bit HD Input and 8-Bit
SD Input Capture Port
– Two 165-MHz HD Video Display Outputs
• One 16-, 24-, or 30-Bit and One 16- or 24-
Bit Output
– Component HD Analog Output
– Composite Analog Output
– Digital HDMI 1.3 Transmitter with Integrated
PHY
– Advanced Video Processing Features Such
as Scan, Format, and Rate Conversion
– Three Graphics Layers and Compositors
• 32-Bit DDR2, DDR3, and DDR3L SDRAM
Interface
– Image Pipe (IPIPE) for Real-Time Image and
Video Processing
– Supports up to 400 MHz for DDR2, 533 MHz
for DDR3, and 533 MHz for DDR3L
– Resizer
• Resizing Image and Video From 1/16x to
8x
– Up to Two x 16 Devices, 2GB of Total
Address Space
– Dynamic Memory Manager (DMM)
• Generating Two Different Resizing
Outputs Concurrently
• Programmable Multi-Zone Memory
Mapping
• Hardware 3A Engine (H3A) for Generating
Key Statistics for 3A (AE, AWB, and AF)
Control
• Face Detect (FD) Engine
• Enables Efficient 2D Block Accesses
• Supports Tiled Objects in 0°, 90°, 180°, or
270° Orientation and Mirroring
– Hardware Face Detection for up to 35 Faces
Per Frame
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PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated