DLPR910_17 Datasheet, PDF (1/17 Pages) Texas Instruments – Configuration PROM

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DLPR910
DLPS065B – SEPTEMBER 2015 – REVISED NOVEMBER 2016
DLPR910 Configuration PROM
1 Features
•1 Pre-Programmed Xilinx^® PROM Configures the
DLPC910ZYR
• Data Transfer Up to 33 Mbps
• I/O Pins Compatible With 1.8 V to 3.3 V
• 1.8-V Core Supply Voltage
• –40°C to 85°C Operating Temperature Range
2 Applications
• Lithography
– Direct Imaging
– Flat Panel Display
– Printed Circuit Board Manufacturing
• Industrial
– 3D Printing
– 3D Scanners for Machine Vision
– Quality Control
• Displays
– 3D Imaging
– Intelligent and Adaptive Lighting
– Augmented Reality and Information Overlay
3 Description
The DLPR910 device is a programmed PROM used
for properly configuring the DLPC910, which supports
reliable operation of the DLP9000X digital micromirror
device (DMD) and the DLP6500 family of DMDs. The
DLPR910 configuration enables the DLPC910 to
operate the DMDs at a pixel data rate greater than 61
Gigabits per second (Gbps) for the DLP9000X and up
to 24 Gbps for the DLP6500 family, with the option
for random row addressing and Load4 capabilities.
The DLPR910 device is part of a multiple component
chipset in the DLP^® Advanced Light Control portfolio.
A dedicated chipset provides developers easier
access to the DMD as well as high speed,
independent micromirror control.
The DLPC910 configuration program is only available
within the DLPR910. The DLPR910 requires that it be
used in conjunction with the DLPC910 and the
DLP9000X DMD or the DLP6500 family of DMDs for
reliable function and operation of the chipset.
For complete electrical and mechanical specifications
of the DLPR910, see the XCF16P product
specification at www.xilinx.com.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DLPR910
DSBGA (48)
8.00 mm × 9.00 mm ×
1.20 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Figure 1. Typical Application Diagram
LVDS Interface
Illumination
Driver
Row and Block Signals
Control Signals
Illumination
Sensor
Status Signals
LVD Interface
JTAG(3:0)
DLPR910 PGM(4:0)
DLPC910
RESET Signals
SCP Interface
DLP9000X
DLP6500
CTRL_RSTZ
I2C
OSC
50 MHz
VLED0
VLED1
Power Management
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.