DLPC910 Datasheet, PDF (1/50 Pages) Texas Instruments – Digital Controller for the DLP9000XFLS Digital Micromirror Device

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DLPC910
DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015
DLPC910 Digital Controller for the DLP9000XFLS Digital Micromirror Device (DMD)
1 Features
•1 Required for Reliable Operation of the
DLP9000XFLS DMD
• User-Selectable 400-MHz and 480-MHz Input
Clock Rate
• Pixel Data Rate Greater than 61 Gigabits Per
Second With Continuous Streaming Input Data
• Enables High-Speed Pattern Rates up to 15 kHz
Binary Patterns per Second
• 8-Bit Gray Scale Pattern Rates up to 1.8 kHz With
Modulated Illumination
• 64-Bit 2x LVDS Data Bus Interface
• Supports Random DMD Row Addressing and
Load4 Loading
• Compatible With a Variety of User-Defined
Application Processors or FPGAs
• Integrated I²C Interface for General Control and
Status Queries
2 Applications
• Lithography
– Direct Imaging
– Flat Panel Display
– Printed Circuit Board Manufacturing
• Industrial
– 3D Printing
– 3D Scanners for Machine Vision
– Quality Control
• Displays
– 3D Imaging
– Augmented Reality and Information Overlay
3 Description
The DLPC910 device is required for reliable operation
of the DLP9000XFLS DMD. This device enables one
of the highest performing DLP^® chipsets.
The DLPC910 provides a high-speed data and
control interface for the DLP9000XFLS DMD enabling
binary pattern rates of up to 15 kHz. These fast
pattern rates set DLP technology apart from other
spatial light modulators and offer customers a
strategic advantage for equipment needing fast,
accurate, and programmable light steering capability.
The DLPC910 provides the required mirror clocking
pulses and timing information to the DMD. The
unique capability and value offered by the DLPC910
device makes it well suited to support a wide variety
of lithography, industrial, and advanced display
applications.
In DLP-based electronics solutions, image data is
100% digital from the DLPC910 input port to the
projected image. The image stays in digital form and
is never converted into an analog signal. The
DLPC910 processes the digital input image and
converts the data into a format needed by the DMD
for proper display. The DMD then steers the light to
the location determined by the pixel data loaded into
the DMD.
For complete electrical and mechanical specifications
of the DLPC910, see the Virtex^®-5 product
specification at www.xilinx.com.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DLPC910
FCBGA (676)
27.00 mm × 27.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Diagram
LVDS Interface
Row and Block Signals
Illumination
Driver
Illumination
Sensor
Control Signals
Status Signals
JTAG(3:0)
DLPR910
PGM(4:0)
CTRL_RSTZ
I2C
OSC
50 MHz
DLPC910
LVD Interface
RESET Signals
SCP Interface
VLED0
VLED1
DLP9000XFLS
Power Management
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.