DLPC3437 Datasheet, PDF (1/9 Pages) Texas Instruments – Display Controller

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DLPC3437 Display Controller
DLPC3437
DLPS090 – JANUARY 2017
1 Features
•1 Display Controller for DLP3310 (.33 1080p) TRP
DMD
– Dedicated 2xDLPC3437 Controller to Drive
DLP3310 DMD
– Supports Input Image Sizes up to 1080p
– Low-Power DMD Interface with Interface
Training
• 24-Bit, Input Pixel Interface Support:
– Parallel Interface
– Pixel Clock up to 150 MHz
• Dual FPD-Link Input Pixel Interface Support:
– LVDS Interface
– Effective Pixel Clock up to 150 MHz
• Pixel Data Processing:
– IntelliBright™ Suite of Image Processing
Algorithms
– Content Adaptive Illumination Control
– Local Area Brightness Boost
– Color Coordinate Adjustment
– Programmable Degamma
– Active Power Management Processing
• Package:
– 201-Pin, 13 mm × 13 mm, 0.8-mm Pitch,
NFBGA
• External Flash Support
• Compatible with the DLPA3000 PMIC/LED Driver
• Auto DMD Parking at Power Down
• Embedded Frame Memory (eDRAM)
• System Features:
– I²C Control of Device Configuration
– Programmable Splash Screens
– Programmable LED Current Control
– One Frame Latency
2 Applications
• Mobile Smart TVs
• Screenless TVs
• Gaming Displays
• Digital Signage
• Wearable Displays
• Pico Projectors
• Interactive Displays
• Ultra Mobile Displays
• Smart Home Displays
3 Description
The DLPC3437 digital controller, part of the DLP3310
(.33 1080p) chipset, supports reliable operation of the
DLP3310 digital micromirror device (DMD). The
DLP3310 chipset enables small form factor, low
power, and high resolution full HD displays.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DLPC3437
NFBGA (201)
13.00 mm × 13.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
DC_IN
BAT
6-20VDC
Charger
DC
Supplies
On/Off
VDD
HDMI _HDMI
Receiver
VGA
Triple
ADC
FLASH,
SDRAM
Keypad
SD Card
Reader,
Video
Decoder,
etc.
PROJ_ON
Front-End
Chip
- OSD
- AutoLock
- Scaler
- uController
HOST_IRQ
I2C
3DR
Parallel
28
FPD-Link
DSI I/F, CPU I/F, and BT656 I/F
are not supported for dual ASIC.
Included in DLP® Chip Set
Non-TI components
Projector Module Electronics
DC
Reg
1.8V
Reg
L5 _{Fan or a programmable}
DC supply
1.8V for DMD and
L4 ^DPP3439s
Frame
Memory
Flash
1.8V
1.1V
XPR FPGA
XC7Z020-
1CLG484I4493
VCC_INTF
I2C_0
I2C_1
VCC_FMEM
SPI
VCC_FLSH
SPI
VIO
VCORE
Flash
1.8V
1.1V
3DR
Parallel
VIN
SYSPWR
PROJ_ON
1.1V
Reg L3
LDO#1
LDO#2
1.1V for DPP3437s
3.3V (to front-end chip)
2.5V (to front-end chip)
GPIO_8
(Normal Park)
1.8V
DLPA3000
VSPI
VLED
Current
L1 Sense
VCC_FLSH
SPI_0
SPI_1
VIO
VCORE PARKZ
I2C_0
DLPC3437
eDRAM
PAD Control 4
RESETZ
INTZ
LED_SEL(2)
CMP_PWM
CMP_OUT
L2
RED
GREEN
V^BB^LI^UA^ES, VRST,
3 VOFS
WPC
LABB
Illumination
Optics
Thermistor
Sub-LVDS DATA
LS CTRL
0.33
W10V8G0PA
DDDRMDDMD
ACT_SYNC
FPGA_RDY
VCC_INTF
GPIO_14-19
Image
Sync
I2C_1
Oscillator
GPIO_09
HOST_IRQ
I2C_0
PARKZ
3DR
Parallel
DAC_Data
DAC_CLK
RESETZ
Actuator
Drive
Circuit
Flash
I2C_1
DLPC3437
eDRAM
VCC_INTF
1.8V
1.1V
VCC_FLSH
SPI_0
VIO
VCORE
3D L/R
RESETZ
INTZ
LS_RDATA
Sub-LVDS DATA
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.