DLPC100 Datasheet, PDF (1/25 Pages) Texas Instruments – DLP® Digital Controller for the DLP1700 DMD

DLPC100
www.ti.com
DLPS019B – DECEMBER 2009 – REVISED DECEMBER 2010
DLP^® Digital Controller for the DLP1700 DMD
Check for Samples: DLPC100
FEATURES
1
• Optimized to Operate With DLPR100 and
DLP1700
• Single 24-Bit Input Port (RGB or BT656-YUV)
With Pixel Clock Support up to 30 MHz
• Input Image Size 320 x 240 (QVGA), 480 x 320
(HVGA), or 640 x 480 (VGA)
• Three RGB Input Color Bit-Depth Options:
RGB888, RGB666, RGB565
• Supports 1 Hz to 60 Hz Frame Rates
• I²C Control Interface for Device Configuration
• Pixel Data Processing:
– Color Space Conversion
– Chroma Interpolation for 4:2:2 to 4:4:4
Conversion
– Color Coordinate Adjustment
– Image Resizing (Scaling)
– De-Interlacing Via Field Scaling
– Frame Rate Conversion
– LED Current Control Adjustment
– Programmable Degamma
– Spatial-Temporal Multiplexing (Dithering)
– Automatic Gain Control
• 60 MHz Double Data Rate (DDR) DMD Interface
• External Memory Support: 100 MHz SDR
SDRAM
• Serial FLASH Interface
• System Control:
– Programmable LED Currents
– DMD Power and Reset Driver Control
– DMD Horizontal and Vertical Image Flip
– Built-in Test Pattern Generation
• JTAG with Boundary Scan Test Support
• Packaged in 256-Pin Ultra Fineline Ball-Grid
Array (uBGA)
DESCRIPTION
The DLPC100 performs all the image processing and control, along with DMD data formatting, for driving a 0.17
HVGA DMD (DLP1700).
The DLPC100 is one of three components in the 0.17 HVGA Chipset (see Figure 1). Proper function and
operation of the DLP1700 requires that it be used in conjunction with the other components of the 0.17 HVGA
Chip-Set. Refer to the 0.17 HVGA Chip-Set Data Sheet for further details (TI literature number DLPS017).
In DLP electronics solutions, image data is 100% digital from the DLPC100 input port to the image projected on
to the display screen. The image stays in digital form and is never converted into an analog signal. The
DLPC100 processes the digital input image and converts the data into a format needed by the DMD. The DMD
then reflects light to the screen using binary pulse-width-modulation (PWM) for each pixel mirror.
Commands can be input to the DLPC100 over an I²C interface.
The digital input interface switching levels, for image data, is nominally 1.8 V, 2.5 V, or 3.3 V. The switching level
used is selected by setting pin INTFPWR to 1.8 V, 2.5 V, or 3.3 V. The input image interface and I²C interface
switching levels must be the same.
Related Documents
DOCUMENT
DLP 0.17 HVGA Chip-Set data sheet
DLPR100 Configuration PROM data sheet
DLP1700 0.17 HVGA DMD data sheet
TI LITERATURE NUMBER
DLPS017
DLPS020
DLPS018
1
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Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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