DLP1700 Datasheet, PDF (1/25 Pages) Texas Instruments – DLP® 0.17 HVGA DDR Series 210 DMD

DLP1700
www.ti.com
DLPS018B – DECEMBER 2009 – REVISED SEPTEMBER 2011
DLP^® 0.17 HVGA DDR Series 210 DMD
Check for Samples: DLP1700
FEATURES
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•2 0.17-Inch Micromirror Array Diagonal
– 480 × 320 Array of Aluminum,
Micrometer-Sized Mirrors
(Half-VGA Resolution )
– 7.6-µm Micromirror Pitch
– ±12° Micromirror Tilt Angle
(Relative to Flat State)
– Designed for Corner Illumination
• Designed for Use With Broadband Visible
Light (420 nm–720 nm):
– Window Transmission 97% (Single Pass,
Through Two Window Surfaces)
– Micromirror Reflectivity 88%
– Array Diffraction Efficiency 86%
– Array Fill Factor 92%
• 10-Bit, Double Data Rate (DDR) Input Data Bus
• 60 MHz Input Data Clock Rate
• Electrical Power Consumption as
Low as 84 mW
• Built-In Reset Driver Circuitry
• 15.5 mm by 9 mm Package Footprint
• Package Includes a 46-pin Board-to-Board
Connector
• Package Mates to a PANASONIC
AXK5L46347G Socket
APPLICATIONS
• Structured Light
• 3D Optical Measurement Systems
• Augmented Reality
• Portable Embedded Displays
DESCRIPTION
The DLP1700 Digital Micromirror Device (DMD) is a digitally controlled MOEMS (micro-opto-electromechanical
system) spatial light modulator (SLM). When coupled to an appropriate optical system, the DLP1700 can be used
to modulate the amplitude, direction, and/or phase of incoming (illumination) light.
Architecturally, the DLP1700 is a latchable, electrical-in/optical-out semiconductor device. This architecture
makes the DLP1700 well suited for use in applications such as structured lighting, 3D optical metrology,
augmented reality, microscopy, and spectroscopy. The compact physical size of the DLP1700 enables
integration into portable equipment.
The DLP1700 is one of three components in the DLP 0.17 HVGA chip-set (see Figure 1). Proper function and
operation of the DLP1700 requires that it be used in conjunction with the other components of the chip-set. Refer
to DLP 0.17 HVGA chip-set data sheet (TI literature number DLPS017) for further details.
Electrically, the DLP1700 consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a square
grid of 480 memory cell columns by 320 memory cell rows. The CMOS memory array is written to on a
column-by-column basis, over a 10-bit double data rate (DDR) bus. Row addressing is handled via a serial
control bus. The specific CMOS memory access protocol is handled by the DLPC100 Digital Controller.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DLP is a registered trademark of Texas Instruments.
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2011, Texas Instruments Incorporated