CY74FCT821T_16 Datasheet, PDF (1/14 Pages) Texas Instruments – 10-BIT BUS-INTERFACE REGISTER WITH 3-STATE OUTPUTS

D Function, Pinout, and Drive Compatible
With FCT, F Logic, and AM29821
D Reduced V_OH (Typically = 3.3 V) Version of
Equivalent FCT Functions
D Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D I_off Supports Partial-Power-Down Mode
Operation
D Matched Rise and Fall Times
D Fully Compatible With TTL Input and
Output Logic Levels
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D 64-mA Output Sink Current
32-mA Output Source Current
D High-Speed Parallel Register With
Positive-Edge-Triggered D-Type Flip-Flops
D 3-State Outputs
CY74FCT821T
10-BIT BUS-INTERFACE REGISTER
WITH 3-STATE OUTPUTS
SCCS033B– MAY 1994 – REVISED NOVEMBER 2001
P, Q, OR SO PACKAGE
(TOP VIEW)
OE 1
D₀ 2
D₁ 3
D₂ 4
D₃ 5
D₄ 6
D₅ 7
D₆ 8
D₇ 9
D₈ 10
D₉ 11
GND 12
24 V_CC
23 Y₀
22 Y₁
21 Y₂
20 Y₃
19 Y₄
18 Y₅
17 Y₆
16 Y₇
15 Y₈
14 Y₉
13 CP
description
This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and
provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT821T is a
10-bit-wide buffered version of the popular CY74FCT374 function. This device is ideal for use as an output port
requiring high I_OL/I_OH.
This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading
at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
PIN DESCRIPTION
NAME I/O
DESCRIPTION
D
I
D flip-flop data inputs
CP
O
Clock pulse for the register. Enters data into the register on the low-to-high clock transition.
Y
O
Register 3-state outputs
OE
I
Output control. When OE is high, the Y outputs are in the high-impedance state.
When OE is low, true register data is present at the Y outputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2001, Texas Instruments Incorporated
1