CY74FCT16841T_15 Datasheet, PDF (1/20 Pages) Texas Instruments – 20-Bit Latches

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT16841T
CY74FCT162841T
SCCS067A - July 1994 - Revised October 2001
20-Bit Latches
Features
• FCT-C speed at 5.5 ns (FCT16841T Com’l)
• I_off supports partial-power-down mode operation
• Edge-rate control circuitry for significantly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of −40˚C to +85˚C
• V_CC = 5V ± 10%
CY74FCT16841T Features:
• 64 mA sink current, 32 mA source current
• Typical V_OLP (ground bounce) <1.0V at V_CC = 5V,
T_A = 25˚C
CY74FCT162841T Features:
• Balanced 24 mA output drivers
• Reduced system switching noise
• Typical V_OLP (ground bounce) <0.6V at V_CC = 5V,
T_A= 25˚C
Functional Description
The CY74FCT16841T and CY74FCT162841T are 20-bit
D-type latches designed for use in bus applications requiring
high speed and low power. These devices can be used as two
independent 10-bit latches, or as a single 10-bit latch, or as a
single 20-bit latch by connecting the Output Enable (OE) and
Latch (LE) inputs. Flow-through pinout and small shrink
packaging aid in simplifying board layout.
This device is fully specified for partial-power-down
applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device
when it is powered down.
The CY74FCT16841T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162841T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162841T is ideal for driving transmission lines.
Logic Block Diagrams
1^OE
1^LE
1^D1
D
1^Q1
C
2^OE
2^LE
2^D1
TO 9 OTHER CHANNELS
FCT16841-1
D
2^Q1
C
TO 9 OTHER CHANNELS
FCT16841-2
Pin Configuration
SSOP/TSSOP
Top View
1^OE 1
1^Q1 2
1^Q2 3
GND 4
1Q3 ⁵
1^Q4 6
V_{CC 7}
1^Q5 ₈
1^Q6 9
1^Q7 ₁₀
GND ₁₁
1^Q8 12
1^Q9 13
1^Q10 14
2^Q1 ¹⁵
2^Q2 16
2^Q3 ¹⁷
GND 18
2^Q4 ¹⁹
2^Q5 ²⁰
2^Q6 ²¹
V_CC 22
2^Q7 23
2^Q8 ²⁴
GND ²⁵
2^Q9 ²⁶
2^Q10 ²⁷
2^{OE 28}
56
1^LE
55
1^D1
54
1^D2
53
GND
52
1^D3
51
1^D4
50
V_CC
49
1^D5
48
1^D6
47
1^D7
46
GND
45
1^D8
44
1^D9
43
1^D10
42
2^D1
41
2^D2
40
2^D3
39
GND
38
2^D4
37
2^D5
36
2^D6
35
V_CC
34
2^D7
33
2^D8
32
GND
31
2^D9
30
2^D10
29
2^LE
FCT16841-3
Copyright © 2001, Texas Instruments Incorporated