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CY74FCT163245_05 Datasheet, PDF (1/10 Pages) Texas Instruments – 16-Bit Transceivers
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT163245
CY74FCT163H245
SCCS051 - February 1997 - Revised March 2000
16-Bit Transceivers
Features
• Low power, pin-compatible replacement for LCX and
LPT families
• 5V tolerant inputs and outputs
• 24 mA balanced drive outputs
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 4.1 ns
• Latch-up performance exceeds JEDEC standard no. 17
• Typical output skew < 250ps
• Industrial temperature range of –40˚C to +85˚C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
• Typical Volp (ground bounce) performance exceeds Mil
Std 883D
• VCC = 2.7V to 3.6V
• ESD (HBM) > 2000V
CY74FCT163H245
• Bus hold on data inputs
• Eliminates the need for external pull-up or pull-down
resistors
• Devices with bus hold are not recommended for trans-
lating rail-to-rail CMOS signals to 3.3V logic levels
Functional Description
These 16-bit transceivers are designed for use in bidirectional
synchronous communication between two buses, where high
speed and low power are required. Direction of data flow is
controlled by (DIR), the Output Enable (OE) transfers data
when LOW and isolates the buses when HIGH. The outputs
are 24-mA balanced output drivers with current limiting
resistors to reduce the need for external terminating resistors
and provide for minimal undershoot and reduced ground
bounce..
The CY74FCT163H245 has “bus hold” on the data inputs,
which retains the input’s last state whenever the input goes to
high impedance. This eliminates the need for pull-up/down
resistors and prevents floating inputs.
The CY74FCT163245 is designed with inputs and outputs
capable of being driven by 5.0V buses, allowing its use in
mixed voltage systems as a translator. The outputs are also
designed with a power off disable feature enabling its use in
applications requiring live insertion.
Logic Block Diagrams CY74FCT163245, CY74FCT163H245
1DIR
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1OE
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2DIR
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2OE
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
Pin Configuration
SSOP/TSSOP
Top View
1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
1
48
2
47
3
46
4
45
5
44
6
43
7 163245 42
8 163H245 41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
Copyright © 2000, Texas Instruments Incorporated