CY74FCT16244T_15 Datasheet, PDF (1/15 Pages) Texas Instruments – 16-Bit Buffers/Line Drivers

1CY74FCT16444T/2
H244T
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT16244T
CY74FCT162244T
CY74FCT162H244T
SCCS028B - December 1987 - Revised September 2001
Features
• I_off supports partial-power-down mode operation
• Edge-rate control circuitry for significantly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of –40˚C to +85˚C
• V_CC = 5V ± 10%
CY74FCT16244T Features:
• 64 mA sink current, 32 mA source current
• Typical V_OLP (ground bounce)
<1.0V at V_CC = 5V, T_A = 25˚C
CY74FCT162244T Features:
• Balanced output drivers: 24 mA
• Reduced system switching noise
• Typical V_OLP (ground bounce)
<0.6V at V_CC = 5V, T_A= 25˚C
CY74FCT162H244T Features:
• Bus hold on data inputs
• Eliminates the need for external pull-up or pull-down
resistors
16-Bit Buffers/Line Drivers
Functional Description
These 16-bit buffers/line drivers are designed for use in
memory driver, clock driver, or other bus interface applications,
where high-speed and low power are required. With
flow-through pinout and small shrink packaging board layout
is simplified. The three-state controls are designed to allow
4-bit, 8-bit or combined 16-bit operation.
This device is fully specified for partial-power-down
applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device
when it is powered down.
The CY74FCT16244T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162244T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for mini-
mal undershoot and reduced ground bounce. The
CY74FCT162244T is ideal for driving transmission lines.
The CY74FCT162H244T is a 24-mA balanced output part that
has “bus hold” on the data inputs. The device retains the in-
put’s last state whenever the input goes to high impedance.
This eliminates the need for pull-up/down resistors and pre-
vents floating inputs.
Logic Block Diagrams CY74FCT16244T, CY74FCT162244T,
CY74FCT162H244T
1^OE
3^OE
1^A1
1^Y1
3^A1
3^Y1
1^A2
1^Y2
3^A2
3^Y2
1^A3
1^Y3
3^A3
3^Y3
1^A4
1^Y4
3^A4
FCT16244–1
3^Y4
FCT16244–2
2^OE
2^A1
2^A2
2^A3
2^A4
2^Y1
2^Y2
2^Y3
2^Y4
FCT16244–3
4^OE
4^A1
4^A2
4^A3
4^A4
4^Y1
4^Y2
4^Y3
4^Y4
FCT16244–4
Pin Configuration
SSOP/TSSOP
Top View
1^OE
1^Y1
1^Y2
GND
1^Y3
1^Y4
V_CC
2^Y1
2^Y2
GND
2^Y3
2^Y4
3^Y1
3^Y2
GND
3^Y3
3^Y4
V_CC
4^Y1
4^Y2
GND
4^Y3
4^Y4
4^OE
1
48
2
47
3
46
4
45
5 ^16244T 44
162244T
6 _162H244T43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2^OE
1^A1
1^A2
GND
1^A3
1^A4
V_CC
2^A1
2^A2
GND
2^A3
2^A4
3^A1
3^A2
GND
3^A3
3^A4
V_CC
4^A1
4^A2
GND
4^A3
4^A4
3^OE
FCT16244–5
Copyright © 2001, Texas Instruments Incorporated