CY54FCT841T_09 Datasheet, PDF (1/12 Pages) Texas Instruments – 10-BIT LATCHES WITH 3-STATE OUTPUTS

D Function, Pinout, and Drive Compatible
With FCT, F, and AM29841 Logic
D Reduced V_OH (Typically = 3.3 V) Versions of
Equivalent FCT Functions
D Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D I_off Supports Partial-Power-Down Mode
Operation
D Matched Rise and Fall Times
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D Fully Compatible With TTL Input and
Output Logic Levels
D High-Speed Parallel Latches
D Buffered Common Latch-Enable Input
D 3-State Outputs
D CY54FCT841T
– 32-mA Output Sink Current
– 12-mA Output Source Current
D CY74FCT841T
– 64-mA Output Sink Current
– 32-mA Output Source Current
CY54FCT841T, CY74FCT841T
10-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001
CY54FCT841T . . . D PACKAGE
CY74FCT841T . . . P, Q, OR SO PACKAGE
(TOP VIEW)
OE 1
D₀ 2
D₁ 3
D₂ 4
D₃ 5
D₄ 6
D₅ 7
D₆ 8
D₇ 9
D₈ 10
D₉ 11
GND 12
24 V_CC
23 Y₀
22 Y₁
21 Y₂
20 Y₃
19 Y₄
18 Y₅
17 Y₆
16 Y₇
15 Y₈
14 Y₉
13 LE
description
The ’FCT841T bus-interface latches are designed to eliminate additional packages required to buffer existing
latches and provide additional data width for wider address/data paths or buses carrying parity. The ’FCT841T
devices are buffered 10-bit-wide versions of the FCT373 function.
The ’FCT841T devices’ high-performance interface is designed for high-capacitance-load drive capability, while
providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance
bus loading in the high-impedance state.
These devices are fully specified for partial-power-down applications using I_off. The I_off circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
NAME
D
LE
Y
OE
PIN DESCRIPTION
I/O
DESCRIPTION
I Latch data inputs
I
Latch-enable input. The latches are transparent when LE is high.
Input data is latched on the high-to-low transition.
O 3-state latch outputs
I
Output-enable control. When OE is low, the outputs are enabled.
When OE is high, the outputs are in the high-impedance (off) state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2001, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1