CLC411 Datasheet, PDF (1/14 Pages) National Semiconductor (TI) – High-Speed Video Op Amp with Disable

OBSOLETE
CLC411
www.ti.com
SNOS829D – AUGUST 2000 – REVISED APRIL 2013
CLC411 High Speed Video Op Amp with Disable
Check for Samples: CLC411
FEATURES
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•2 200MHz Small Signal Bandwidth (1V_PP)
• ±0.05dB Gain Flatness to 30MHz
• 0.02%, 0.03° Differential Gain, Phase
• 2300V/µs Slew Rate
• 10ns Disable to High Impedance Output
• 70mA Continuous Output Current
• ±4.5V Output Swing into 100Ω Load
• ±4.0V Input Voltage Range
APPLICATIONS
• HDTV Amplifier
• Video Line Driver
• High Speed Analog Bus Driver
• Video Signal Multiplexer
• DAC Output Buffer
DESCRIPTION
The CLC411 combines a state-of-the-art
complementary bipolar process with TI's patented
current feedback architecture to provide a very high
speed op amp operating from ±15V supplies. Drawing
only 11mA quiescent current, the CLC411 provides a
200MHz small signal bandwidth and a 2300V/µs slew
rate while delivering a continuous 70mA current
output with ±4.5V output swing. The CLC411's high
speed performance includes a 15ns settling time to
0.1% (2V step) and a 2.3ns rise and fall time (6V
step).
The CLC411 is designed to meet the requirements of
professional broadcast video systems including
composite video and high definition television. The
CLC411 exceeds the HDTV standard for gain flatness
to 30MHz with it's ±0.05dB flat frequency response
and exceeds composite video standards with its very
low differential gain and phase errors of 0.02%, 0.03°.
The CLC411 is the op amp of choice for all video
systems requiring upward compatibility from NTSC
and PAL to HDTV.
The CLC411 features a very fast disable/enable
(10ns/55ns) allowing the multiplexing of high speed
signals onto an analog bus through the common
output connections of multiple CLC411's. Using the
same signal source to drive disable/enable pins is
easy since "break-before-make" is ensured.
Enhanced Solutions (Military/Aerospace)
SMD Number: 5962-94566
Space level versions also available.
Gain Flatness (A_V=+2)
CONNECTION DIAGRAM
Figure 1. Pinout
PDIP & SOIC
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