CDCVF2510_17 Datasheet, PDF (1/16 Pages) Texas Instruments – 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

CDCVF2510
www.ti.com
SCAS638C – JULY 2001 – REVISED APRIL 2006
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
FEATURES
• Designed to Meet and Exceed PC133 SDRAM
Registered DIMM Specification Rev. 1.1
• Spread Spectrum Clock Compatible
• Operating Frequency 50 MHz to 175 MHz
• Static Phase Error Distribution at 66 MHz to
166 MHz Is ±125 ps
• Jitter (cyc - cyc) at 66 MHz to 166 MHz
Is |70| ps
• Advanced Deep Submicron Process Results
in More Than 40% Lower Power Consumption
Versus Current Generation PC133 Devices
• Available in Plastic 24-Pin TSSOP
• Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
• Distributes One Clock Input to One Bank of
10 Outputs
• External Feedback (FBIN) Terminal Is Used to
Synchronize the Outputs to the Clock Input
• 25-Ω On-Chip Series Damping Resistors
• No External RC Network Required
• Operates at 3.3 V
PW PACKAGE
(TOP VIEW)
AGND 1
V_CC 2
1Y0 3
1Y1 4
1Y2 5
GND 6
GND 7
1Y3 8
1Y4 9
V_CC 10
G 11
FBOUT 12
24 CLK
23 AV_CC
22 V_CC
21 1Y9
20 1Y8
19 GND
18 GND
17 1Y7
16 1Y6
15 1Y5
14 V_CC
13 FBIN
NOT RECOMMENDED
FOR NEW DESIGNS
USE CDCVF2510A AS
A REPLACEMENT
DESCRIPTION
The CDCVF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a
phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock
(CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2510 operates at a
3.3-V V_CC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of 10 outputs provides 10 low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to
50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When the
G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are
disabled to the logic-low state.
Unlike many products containing PLLs, the CDCVF2510 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDCVF2510 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application of a
fixed-frequency, a fixed-phase signal at CLK, or following any changes to the PLL reference or feedback signals.
The PLL can be bypassed for test purposes by strapping AV_CC to ground.
The CDCVF2510 is characterized for operation from 0°C to 85°C.
For application information see the application reports High Speed Distribution Design Techniques for
CDC509/516/2509/2510/2516 (SLMA003) and Using CDC2509A/2510A PLL With Spread Spectrum Clocking
(SSC) (SCAA039).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2006, Texas Instruments Incorporated