CDCM7005_15 Datasheet, PDF (1/52 Pages) Texas Instruments – 3.3-V High Performance Clock Synchronizer and Jitter Cleaner

Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
Reference
Design
CDCM7005
SCAS793F – JUNE 2005 – REVISED JULY 2015
CDCM7005 3.3-V High Performance Clock Synchronizer and Jitter Cleaner
1 Features
•1 High Performance LVPECL and LVCMOS PLL
Clock Synchronizer
• Two Reference Clock Inputs (Primary and
Secondary Clock) for Redundancy Support With
Manual or Automatic Selection
• Accepts LVCMOS Input Frequencies up to 200
MHz
• VCXO_IN Clock is Synchronized to One of the
Two Reference Clocks
• VCXO_IN Frequencies Up to 2.2 GHz (LVPECL)
• Outputs Can Be a Combination of LVPECL and
LVCMOS (Up to Five Differential LVPECL Outputs
or up to 10 LVCMOS Outputs)
• Output Frequency is Selectable by ×1, /2, /3, /4,
/6, /8, /16 on Each Output Individually
• Efficient Jitter Cleaning From Low PLL Loop
Bandwidth
• Low Phase Noise PLL Core
• Programmable Phase Offset (PRI_REF and
SEC_REF to Outputs)
• Wide Charge Pump Current Range From
200 μA to 3 mA
• Dedicated Charge Pump Supply (VCC_CP) for
Wide Tuning Voltage Range VCOs
• Presets Charge Pump to VCC_CP/2 for Fast
Center-Frequency Setting of VC(X)O
• Analog and Digital PLL Lock Indication
• Provides VBB Bias Voltage Output for Single-
Ended Input Signals (VCXO_IN)
• Frequency Hold-Over Mode Improves Fail-Safe
Operation
• Power-up Control Forces LVPECL Outputs to 3-
State at V_CC < 1.5 V
• SPI Controllable Device Setting
• 3.3-V Power Supply
• Packaged in 64-Pin BGA (0.8 mm Pitch – ZVA) or
48-Pin QFN (RGZ)
• Industrial Temperature Range –40°C to 85°C
3 Description
The CDCM7005 is a high-performance, low phase
noise and low skew clock synchronizer that
synchronizes a VCXO (voltage controlled crystal
oscillator) or VCO (voltage controlled oscillator)
frequency to one of the two reference clocks. The
programmable pre-divider M and the feedback-
dividers N and P give a high flexibility to the
frequency ratio of the reference clock to VC(X)O
VC(X)O_IN clock operates up to 2.2 GHz. Through
the selection of external VC(X)O and loop filter
components, the PLL loop bandwidth and damping
factor can be adjust to meet different system
requirements.
The CDCM7005 can lock to one of two reference
clock inputs (PRI_REF and SEC_REF), supports
frequency hold-over mode and fast-frequency-locking
for fail-safe and increased system redundancy. The
outputs of the CDCM7005 are user definable and can
be any combination of up to five LVPECL outputs or
up to 10 LVCMOS outputs. The built in
synchronization latches ensure that all outputs are
synchronized for low output skew.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CDCM7005
VQFN (48)
BGA (64)
7.00 mm × 7.00 mm
8.00 mm × 8.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
OSC
PRI
REF
VCXO
IN
VCXO
IN
CDCM7005
DAC
YnA
YnB
CP
OUT
VCXO
LF
2 Applications
• Wireless Infrastructure
• SONET
• Data Communication
• Test Equipment
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.