CDCM6208V2G Datasheet, PDF (1/88 Pages) Texas Instruments – CDCM6208V2G 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers

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CDCM6208V2G
SNAS682 – MARCH 2016
CDCM6208V2G 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
1 Features
•1 Superior Performance with Low Power:
– Low Noise Synthesizer (265 fs-rms Typical
Jitter) or Low Noise Jitter Cleaner (1.6 ps-rms
Typical Jitter)
– 0.5 W Typical Power Consumption
– High Channel-to-Channel Isolation and
Excellent PSRR
– Device Performance Customizable Through
Flexible 1.8 V, 2.5 V and 3.3 V Power
Supplies, Allowing Mixed Output Voltages
• Flexible Frequency Planning:
– 4x Integer Down-divided Differential Clock
Outputs Supporting LVPECL-like, CML, or
LVDS-like Signaling
– 4x Fractional or Integer Divided Differential
Clock Outputs Supporting HCSL, LVDS-like
Signaling, or Eight CMOS Outputs
– Fractional Output Divider Achieve 0 ppm to < 1
ppm Frequency Error and Eliminates need for
Crystal Oscillators and Other Clock Generators
– Output frequencies up to 800 MHz
• Two Differential Inputs, XTAL Support, Ability for
Smart Switching
• SPI, I²C™, and Pin Programmable
• Professional user GUI for Quick Design
Turnaround
• 7 x 7 mm 48-QFN package (RGZ)
• -40 °C to 85 °C temperature range
2 Applications
• Base Band Clocking (Wireless Infrastructure)
• Networking and Data Communications
• Keystone C66x Multicore DSP Clocking
• Storage Server, Portable Test Equipment,
• Medical Imaging, High End A/V
3 Description
The CDCM6208V2G is a highly versatile, low jitter,
low-power frequency synthesizer that can generate
eight low jitter clock outputs, selectable between
LVPECL-like high-swing CML, normal-swing CML,
LVDS-like low-power CML, HCSL, or LVCMOS, from
one of two inputs that can feature a low frequency
crystal or CML, LVPECL, LVDS, or LVCMOS signals
for a variety of wireless infrastructure baseband,
wireline data communication, computing, low power
medical imaging and portable test and measurement
applications. The CDCM6208V2G also features an
innovative fractional divider architecture for four of its
outputs that can generate any frequency with better
than 1ppm frequency accuracy. The CDCM6208V2G
can be easily configured through I²C or SPI
programming interface and in the absence of serial
interface, pin mode is also available that can set the
device in 1 of 32 distinct pre-programmed
configurations using control pins.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CDCM6208V2G
VQFN (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematics
CDCM6208
Synthesizer
Mode
DR Packet PCIe
Accel
TMS320TCI6616/18
DSP
Base Band DSP
Clocking
AIF ALT SRIO
CORE
Core
Packet
network
Timing
SyncE
Ethernet
Ethernet
GPS receiver 1pps
IEEE1588
timing extract
DPLL
1pps
Pico Cell Clocking
FBADC
RXADC
TXDAC
CDCM6208
APLL
RF LO
RF LO
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.