CDCLVP2102_16 Datasheet, PDF (1/30 Pages) Texas Instruments – Four-LVPECL Output, High-Performance Clock Buffer

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CDCLVP2102
SCAS881C – AUGUST 2009 – REVISED JANUARY 2016
CDCLVP2102 Four-LVPECL Output, High-Performance Clock Buffer
1 Features
•1 Dual 1:2 Differential Buffer
• Two Clock Inputs
• Universal Inputs Can Accept LVPECL, LVDS,
LVCMOS/LVTTL
• Four LVPECL Outputs
• Maximum Clock Frequency: 2 GHz
• Maximum Core Current Consumption: 48 mA
• Very Low Additive Jitter: <100 fs, RMS in 10-kHz
to 20-MHz Offset Range
• 2.375-V to 3.6-V Device Power Supply
• Maximum Propagation Delay: 450 ps
• Maximum Within Bank Output Skew: 10 ps
• LVPECL Reference Voltage, V_{AC_REF}, Available
for Capacitive-Coupled Inputs
• Industrial Temperature Range: –40°C to +85°C
• Supports 105°C PCB Temperature (Measured
with a Thermal Pad)
• Available in 3-mm × 3-mm, 16-Pin VQFN (RGT)
Package
• ESD Protection Exceeds 2000 V (HBM)
2 Applications
• Wireless Communications
• Telecommunications/Networking
• Medical Imaging
• Test and Measurement Equipment
3 Description
The CDCLVP2102 is a highly versatile, low additive
jitter buffer that can generate four copies of LVPECL
clock outputs from two LVPECL, LVDS, or LVCMOS
inputs for a variety of communication applications. It
has a maximum clock frequency up to 2 GHz. Each
buffer block consists of one input that feeds two
LVPECL outputs. The overall additive jitter
performance is less than 0.1 ps, RMS from 10 kHz to
20 MHz, and overall output skew is as low as 10 ps,
making the device a perfect choice for use in
demanding applications.
The CDCLVP2102 clock buffer distributes two clock
inputs (IN0, IN1) to four pairs of differential LVPECL
clock outputs (OUT0, OUT3) with minimum skew for
clock distribution. Each buffer block consists of one
input that feeds two LVPECL clock outputs. The
inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP2102 is specifically designed for driving
50-Ω transmission lines. When driving the inputs in
single-ended mode, the LVPECL bias voltage
(V_{AC_REF}) should be applied to the unused negative
input pin. However, for high-speed performance up to
2 GHz, differential mode is strongly recommended.
The CDCLVP2102 is characterized for operation from
–40°C to +85°C and is available in a 3-mm × 3-mm,
VQFN-16 package.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CDCLVP2102
VQFN (16)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
V_CC
INP0
INN0
INP1
INN1
LVPECL
LVPECL
OUTP[1,0]
2
OUTN[1,0]
2
OUTP[3,2]
2
OUTN[3,2]
2
V_{AC_REF}
Reference
Generator
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.