CDCLVP1204_15 Datasheet, PDF (1/32 Pages) Texas Instruments – Four LVPECL Output, High-Performance Clock Buffer

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CDCLVP1204
SCAS880F – AUGUST 2009 – REVISED SEPTEMBER 2015
CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer
1 Features
•1 2:4 Differential Buffer
• Selectable Clock Inputs Through Control Terminal
• Universal Inputs Accept LVPECL, LVDS, and
LVCMOS/LVTTL
• Four LVPECL Outputs
• Maximum Clock Frequency: 2 GHz
• Maximum Core Current Consumption: 45 mA
• Very Low Additive Jitter: <100 fs, RMS in 10-kHz
to 20-MHz Offset Range:
– 57 fs, RMS (typical) at 122.88 MHz
– 48 fs, RMS (typical) at 156.25 MHz
– 30 fs, RMS (typical) at 312.5 MHz
• 2.375-V to 3.6-V Device Power Supply
• Maximum Propagation Delay: 450 ps
• Maximum Output Skew: 15 ps
• LVPECL Reference Voltage, V_{AC_REF}, Available
for Capacitive-Coupled Inputs
• Industrial Temperature Range: –40°C to +85°C
• Supports 105°C PCB Temperature (Measured at
Thermal Pad)
• ESD Protection Exceeds 2 kV (HBM)
2 Applications
• Wireless Communications
• Telecommunications/Networking
• Medical Imaging
• Test and Measurement Equipment
3 Description
The CDCLVP1204 is a highly versatile, low additive
jitter buffer that can generate four copies of LVPECL
clock outputs from one of two selectable LVPECL,
LVDS, or LVCMOS inputs for a variety of
communication applications. It has a maximum clock
frequency up to 2 GHz. The CDCLVP1204 features
an on-chip multiplexer (MUX) for selecting one of two
inputs that can be easily configured solely through a
control terminal. The overall additive jitter
performance is less than 0.1 ps, RMS from 10 kHz to
20 MHz, and overall output skew is as low as 15 ps,
making the device a perfect choice for use in
demanding applications.
The CDCLVP1204 clock buffer distributes one of two
selectable clock inputs (IN0, IN1) to four pairs of
differential LVPECL clock outputs (OUT0, OUT3) with
minimum skew for clock distribution. The
CDCLVP1204 can accept two clock sources into an
input multiplexer. The inputs can be LVPECL, LVDS,
or LVCMOS/LVTTL.
The CDCLVP1204 is specifically designed for driving
50-Ω transmission lines. When driving the inputs in
single-ended mode, the LVPECL bias voltage
(V_{AC_REF}) must be applied to the unused negative
input terminal. However, for high-speed performance
up to 2 GHz, differential mode is strongly
recommended.
The CDCLVP1204 is characterized for operation from
–40°C to +85°C.
Device Information⁽¹⁾
PART NUMBER PACKAGE
BODY SIZE (NOM)
CDCLVP1204
QFN (16)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
INP0
INN0
INP1
INN1
IN_SEL
V_{AC_REF}
1
Simplified Schematic
V_CC
LVPECL
OUTP[3...0]
4
OUTN[3...0]
4
Reference
Generator
GND
Differential Output Peak-to-Peak Voltage
vs. Frequency
1.3
1.2
1.1
1.0
0.9
0.8
0.7 _{VCC = 3.0 V}
0.6 T_A = -40°C to +85°C
0.5 ^{VICM = 1 V}
V_IN,DIFF,PP = Min
0.4
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Frequency (GHz)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.