CDCLVD110_12 Datasheet, PDF (1/13 Pages) Texas Instruments – PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER

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CDCLVD110
SCAS684C – SEPTEMBER 2002 – REVISED JANUARY 2008
Not Recommended for New Designs
PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER
FEATURES
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• Low-Output Skew <30 ps (Typical) for
Clock-Distribution Applications
• Distributes One Differential Clock Input to
10 LVDS Differential Clock Outputs
• V_CC range 2.5 V ±5%
• Typical Signaling Rate Capability of Up to
1.1 GHz
• Configurable Register (SI/CK) Individually
Enables Disables Outputs, Selectable CLK0,
CLK0 or CLK1, CLK1 Inputs
• Full Rail-to-Rail Common-Mode Input Range
• Receiver Input Threshold ±100 mV
• Available in 32-Pin LQFP Package
• Fail-Safe I/O-Pins for V_DD = 0 V (Power Down)
LQFP PACKAGE
DESCRIPTION
The CDCLVD110 clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10
pairs of differential clock outputs (Q0, Q9) with minimum skew for clock distribution. The CDCLVD110 is
specifically designed for driving 50-Ω transmission lines.
When the control enable is high (EN = 1), the 10 differential outputs are programmable in that each output can
be individually enabled/disabled (3-stated) according to the first 10 bits loaded into the shift register. Once the
shift register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN = 0, the
outputs are not programmable and all outputs are enabled.
The CDCLVD110 is characterized for operation from –40°C to 85°C.
Not Recommended for New Designs. Use CDCLVD110A as a Replacement.
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2008, Texas Instruments Incorporated