CDCI6214 Datasheet, PDF (1/7 Pages) Texas Instruments – PCIe Gen4 Compliant Ultra-Low Power Clock Generator With Four Programmable Outputs and EEPROM

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CDCI6214
SNAS748 – JULY 2017
CDCI6214 PCIe Gen4 Compliant Ultra-Low Power Clock Generator
With Four Programmable Outputs and EEPROM
1 Features
•1 One Configurable High Performance, Low-Power
PLL With 4 Programmable Outputs
• RMS Jitter Performance
– Supports PCIe Gen1 / Gen2 / Gen3 / Gen4
(500 fs)
• Universal Clock Input
– Differential AC-Coupled or LVCMOS: 1 MHz to
250 MHz
– Crystal: 8 MHz to 50 MHz
• Flexible Output Frequencies
– 44.1 kHz to 350 MHz
– Glitch-Less Output Divider Switching
– Spread Spectrum Clocking (SSC) for PCIe
• Four Individually Configurable Outputs
– LVCMOS, LVDS or HCSL
– Differential AC-Coupled With Programmable
Swing (LVDS-, CML-, LVPECL-Compatible)
• Fully Integrated PLL, Configurable Loop
Bandwidth: 100 kHz to 3 MHz
• Single or Mixed Supply Operation for Level
Translation: 1.8 V, 2.5 V and 3.3 V
• Typical Power Consumption: 150 mW at 1.8 V⁽²⁾
• Configurable GPIOs
– Status Signals
– Up to 4 Individual Output Enables
– Output Divider Synchronization
• Flexible Configuration Options
– I²C-Compatible Interface: Up to 400 kHz
– Integrated EEPROM With Two Pages and
External Select Pin
• Industrial Temperature Range: – 40ºC to 85ºC
• Small Footprint: 24-Pin VQFN (4 mm × 4 mm)
2 Applications
• FPGA, Microcontroller and PCIe Clocking
• Portable Electronics: Cameras, Handheld
Oscilloscope
• Personal Electronics: Printers, Gaming
• Factory Automation and Process Control:
Industrial PC, PLC
• Video Processing and Broadcast
• 1G / 10G Ethernet Switches, NIC, Accelerators
3 Description
The CDCI6214 device is an ultra-low power clock
generator. The device has one phase-locked loop
and generates up to four different frequencies on
configurable differential output channels and also a
copy of the reference clock on a LVCMOS output
channel.
Each of the four output channels has a configurable
integer divider. Together with the output muxes, this
allows up to five different frequencies. The dividers in
the clock distribution path can be reset in a
deterministic way to allow clean clock gating as well
as glitch-less frequency transition when
reprogrammed.
The CDCI6214 is configured using internal registers
that are accessed by an I²C-compatible serial
interface. The device contains two pages in its
internal EEPROM. Each page can contain a device
configuration.
The CDCI6214 enables high-performance clock trees
from a single reference at ultra-low power with a
small footprint. The serial interface and EEPROM
make the CDCI6214 ideal to clock modular and
extendable systems.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CDCI6214
VQFN (24)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Four LVDS outputs, 156.25 MHz with crystal reference.
Application Example CDCI6214
Voltage Domain
1.8V / 2.5V / 3.3V
FPGA
Crystal
CDCI6214
DDAACC
Voltage Domain
1.8V / 2.5V / 3.3V
MCU
Ethernet LVCMOS
Crystal Copy
PCIe
Voltage Domain
1.8V / 2.5V / 3.3V
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.