CDC208_16 Datasheet, PDF (1/18 Pages) Texas Instruments – DUAL 1-LINE TO 4-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

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D Low-Skew Propagation Delay
Specifications for Clock-Driver
Applications
D TTL-Compatible Inputs and
CMOS-Compatible Outputs
D Flow-Through Architecture Optimizes
PCB Layout
D Center-Pin V_CC and GND Pin
Configurations Minimize High-Speed
Switching Noise
D EPIC  (Enhanced-Performance Implanted
CMOS) 1-µm Process
D 500-mA Typical Latch-Up Immunity at
125°C
D Package Options Include Plastic
Small-Outline (DW)
CDC208
DUAL 1ĆLINE TO 4ĆLINE CLOCK DRIVER
WITH 3ĆSTATE OUTPUTS
SCAS109F − APRIL 1990 − REVISED OCTOBER 1998
DW PACKAGE
(TOP VIEW)
1Y2 1
1Y3 2
1Y4 3
GND 4
GND 5
GND 6
GND 7
2Y1 8
2Y2 9
2Y3 10
20 1Y1
19 1A
18 1OE1
17 1OE2
16 V_CC
15 V_CC
14 2A
13 2OE1
12 2OE2
11 2Y4
description
The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew
for clock distribution (see Figure 2). The device also offers two output-enable (OE1 and OE2) inputs for each
circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level
independent of the signal on the respective A input.
Skew parameters are specified for a reduced temperature and voltage range common to many applications.
The CDC208 is characterized for operation from − 40°C to 85°C.
FUNCTION TABLES
INPUTS
OUTPUTS
1OE1 1OE2 1A 1Y1 1Y2 1Y3 1Y4
L
L
L
L
L
L
L
L
L
H
H
H
H
H
L
H
X
L
L
L
L
H
L
X
H
H
H
H
H
H
X
Z
Z
Z
Z
INPUTS
OUTPUTS
2OE1 2OE2 2A 2Y1 2Y2 2Y3 2Y4
L
L
L
L
L
L
L
L
L
H
H
H
H
H
L
H
X
L
L
L
L
H
L
X
H
H
H
H
H
H
X
Z
Z
Z
Z
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1998, Texas Instruments Incorporated
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