CD74FCT543_14 Datasheet, PDF (1/11 Pages) Texas Instruments – BiCMOS OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS

D BiCMOS Technology With Low Quiescent
Power
D Buffered Inputs
D Inverted Outputs
D Input/Output Isolation From V_CC
D Controlled Output Edge Rates
D 64-mA Output Sink Current
D Output Voltage Swing Limited to 3.7 V
D SCR Latch-Up-Resistant BiCMOS Process
and Circuit Design
D Package Options Include Plastic
Small-Outline (M) and Shrink Small-Outline
(SM) Packages and Standard Plastic (EN)
DIP
CD74FCT543
BiCMOS OCTAL REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS742 – JULY 2000
EN, M, OR SM PACKAGE
(TOP VIEW)
LEBA 1
OEBA 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
A8 10
CEAB 11
GND 12
24 V_CC
23 CEBA
22 B1
21 B2
20 B3
19 B4
18 B5
17 B6
16 B7
15 B8
14 LEAB
13 OEAB
description
The CD74FCT543 is an octal register/transceiver with 3-state outputs that uses a small-geometry BiCMOS
technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level
to two diode drops below V_CC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing
[a source of electromagnetic interference (EMI)] and minimizes V_CC bounce and ground bounce and their
effects during simultaneous output switching. The output configuration also enhances switching speed and is
capable of sinking 64 mA.
This device contains two sets of eight D-type latches with separate input and output controls for each set. For
data flow from A to B, for example, the A-to-B enable (CEAB) input must be low to enter data from A1 to A8 or
to take data from B1 to B8. When CEAB is low, a low signal on the A-to-B latch enable (LEAB) input makes the
A-to-B latches transparent; a subsequent low-to-high transition of the LEAB signal puts the A latches in the
storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both low, the B output
buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar,
but uses the CEBA, LEBA, and OEBA inputs.
The CD74FCT543 contains two sets of D-type latches for temporary storage of data flowing in either direction.
Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each
register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and
LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches
in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present
at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and OEBA
inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The CD74FCT543 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 2000, Texas Instruments Incorporated
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