CD74ACT175_14 Datasheet, PDF (1/13 Pages) Texas Instruments – QUADRUPLE D-TYPE FLIP-FLOP

D Inputs Are TTL-Voltage Compatible
D Contains Four Flip-Flops With Double-Rail
Outputs
D Buffered Inputs
D Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
D Balanced Propagation Delays
D ±24-mA Output Drive Current
– Fanout to 15 F Devices
D SCR-Latchup-Resistant CMOS Process and
Circuit Design
D Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
D Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
CD74ACT175
QUADRUPLE D-TYPE FLIP-FLOP
WITH CLEAR
SCHS345 – APRIL 2003
E OR M PACKAGE
(TOP VIEW)
CLR 1
1Q 2
1Q 3
1D 4
2D 5
2Q 6
2Q 7
GND 8
16 V_CC
15 4Q
14 4Q
13 4D
12 3D
11 3Q
10 3Q
9 CLK
description/ordering information
This positive-edge-triggered D-type flip-flop has a direct clear (CLR) input. The CD74ACT175 features
complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not
directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low
level, the D input has no effect at the output.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – E
Tube
CD74ACT175E
CD74ACT175E
–55°C to 125°C
SOIC – M
Tube
CD74ACT175M
Tape and reel CD74ACT175M96
ACT175M
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines}
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
CLR CLK D
Q
Q
L
X
X
L
H
H
↑
H
H
L
H
↑
L
L
H
H
L
X
Q0 Q0
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2003, Texas Instruments Incorporated
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