CD54HC273_16 Datasheet, PDF (1/18 Pages) Texas Instruments – High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset

Data sheet acquired from Harris Semiconductor
SCHS174B
February 1998 - Revised May 2003
CD54HC273, CD74HC273,
CD54HCT273, CD74HCT273
High-Speed CMOS Logic
Octal D-Type Flip-Flop with Reset
[ /Title
(CD74
HC273
,
CD74
HCT27
3)
/Sub-
ject
(High
Speed
CMOS
Logic
Octal
D-
Type
Flip-
Features
Description
• Common Clock and Asynchronous Master Reset
• Positive Edge Triggering
• Buffered Inputs
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC
at V_CC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
The ’HC273 and ’HCT273 high speed octal D-Type flip-flops
with a direct clear input are manufactured with silicon-gate
CMOS technology. They possess the low power consumption
of standard CMOS integrated circuits.
Information at the D inputis transferred to the Q outputs on
the positive-going edge of the clock pulse. All eight flip-flops
are controlled by a common clock (CP) and a common reset
(MR). Resetting is accomplished by a low voltage level
independent of the clock. All eight Q outputs are reset to a
logic 0.
Ordering Information
PART NUMBER
TEMP. RANGE (^oC)
PACKAGE
CD54HC273F3A
-55 to 125
20 Ld CERDIP
CD74HC273E
-55 to 125
20 Ld PDIP
CD74HC273M
-55 to 125
20 Ld SOIC
CD74HC273M96
-55 to 125
20 Ld SOIC
CD54HCT273F3A
-55 to 125
20 Ld CERDIP
CD74HCT273E
-55 to 125
20 Ld PDIP
CD74HCT273M
-55 to 125
20 Ld SOIC
CD74HCT273M96
-55 to 125
20 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
Pinout
CD54HC273, CD54HCT273
(CERDIP)
CD74HC273, CD74HCT273
(PDIP, SOIC)
TOP VIEW
MR 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 V_CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
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