CD54HC112_15 Datasheet, PDF (1/20 Pages) Texas Instruments – Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

Data sheet acquired from Harris Semiconductor
SCHS141H
March 1998 - Revised October 2003
CD54HC112, CD74HC112,
CD54HCT112, CD74HCT112
Dual J-K Flip-Flop with Set and Reset
Negative-Edge Trigger
[ /Title
(CD74
HC112
,
CD74
HCT11
2)
/Sub-
ject
(Dual
J-K
Flip-
Flop
with
Set and
Reset
Nega-
Features
Description
• Hysteresis on Clock Inputs for Improved Noise
Immunity and Increased Input Rise and Fall Times
• Asynchronous Set and Reset
• Complementary Outputs
• Buffered Inputs
• _TTAyp=ic2a5l_ofC_MAX = 60MHz at V_CC = 5V, C_L = 15pF,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC
at V_CC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
Pinout
CD54HC112, CD54HCT112 (CERDIP)
CD74HC112 (PDIP, SOIC, SOP, TSSOP)
CD74HCT112 (PDIP)
TOP VIEW
The ’HC112 and ’HCT112 utilize silicon-gate CMOS
technology to achieve operating speeds equivalent to LSTTL
parts. They exhibit the low power consumption of standard
CMOS integrated circuits, together with the ability to drive 10
LSTTL loads.
These flip-flops have independent J, K, Set, Reset, and
Clock inputs and Q and Q outputs. They change state on the
negative-going transition of the clock pulse. Set and Reset
are accomplished asynchronously by low-level inputs.
The HCT logic family is functionally as well as pin-
compatible with the standard LS logic family.
.
Ordering Information
PART NUMBER
TEMP. RANGE
(^oC)
PACKAGE
CD54HC112F3A
-55 to 125
16 Ld CERDIP
CD54HCT112F3A
-55 to 125
16 Ld CERDIP
CD74HC112E
-55 to 125
16 Ld PDIP
CD74HC112MT
-55 to 125
16 Ld SOIC
CD74HC112M96
-55 to 125
16 Ld SOIC
CD74HC112NSR
-55 to 125
16 Ld SOP
CD74HC112PW
-55 to 125
16 Ld TSSOP
CD74HC112PWR
-55 to 125
16 Ld TSSOP
CD74HC112PWT
-55 to 125
16 Ld TSSOP
CD74HCT112E
-55 to 125
16 Ld PDIP
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
1CP 1
1K 2
1J 3
1S 4
1Q 5
1Q 6
2Q 7
GND 8
16 V_CC
15 1R
14 2R
13 2CP
12 2K
11 2J
10 2S
9 2Q
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
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