CD54AC163_14 Datasheet, PDF (1/19 Pages) Texas Instruments – 4-BIT SYNCHRONOUS BINARY COUNTERS

CD54AC163, CD74AC163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS299B – APRIL 2000 – REVISED MARCH 2003
D Internal Look-Ahead for Fast Counting
D Carry Output for n-Bit Cascading
D Synchronous Counting
D Synchronously Programmable
CD54AC163 . . . F PACKAGE
CD74AC163 . . . E OR M PACKAGE
(TOP VIEW)
CLR 1
CLK 2
16 V_CC
15 RCO
description/ordering information
The ’AC163 devices are 4-bit binary counters.
These synchronous, presettable counters feature
an internal carry look-ahead for application in
A3
B4
C5
D6
ENP 7
14 Q_A
13 Q_B
12 Q_C
11 Q_D
10 ENT
high-speed counting designs. Synchronous
operation is provided by having all flip-flops
GND 8
9 LOAD
clocked simultaneously so that the outputs
change, coincident with each other, when instructed by the count-enable (ENP, ENT) inputs and internal gating.
This mode of operation eliminates the output counting spikes normally associated with synchronous
(ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge
of the clock waveform.
The counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15.
Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes
the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function is synchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low
after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear
allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The
active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000
(LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15, with Q_A high). This high-level overflow ripple-carry pulse
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
These devices feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – E Tube
CD74AC163E
CD74AC163E
Tube
–55°C to 125°C SOIC – M
Tape and reel
CD74AC163M
AC163M
CD74AC163M96
CDIP – F Tube
CD54AC163F3A CD54AC163F3A
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB}
design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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