AM4382 Datasheet, PDF (1/18 Pages) Texas Instruments – Sitara Processors Technical Brief

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AM4382, AM4384, AM4388
SPRT726A – MARCH 2017 – REVISED APRIL 2017
AM438x Sitara™ Processors Technical Brief
1 Device Overview
1.1 Features
1
• Highlights
– Sitara™ ARM^® Cortex^®-A9 32-Bit RISC
Processor With Processing Speed up to
1000 MHz
– NEON™ SIMD Coprocessor and Vector
Floating Point (VFPv3) Coprocessor
– 32KB of Both L1 Instruction and Data Cache
– 256KB of L2 Cache or L3 RAM
– 32-Bit LPDDR2, DDR3, and DDR3L Support
– General-Purpose Memory Support (NAND,
NOR, SRAM) Supporting up to 16-Bit ECC
– SGX530 Graphics Engine
– Display Subsystem
– Programmable Real-Time Unit Subsystem and
Industrial Communication Subsystem (PRU-
ICSS)
– Real-Time Clock (RTC)
– Up to Two USB 2.0 High-Speed Dual-Role
(Host or Device) Ports With Integrated PHY
– 10, 100, and 1000 Ethernet Switch
– Serial Interfaces:
– Six UARTs, Two McASPs, Five McSPIs,
Three I²C Ports, One QSPI, and One HDQ or
1-Wire
– Up to Two ISO7816 (Smart Card) Interfaces
– Security
– Crypto Hardware Accelerators (AES, SHA,
PKA, RNG, DES, and 3DES) With Crypto
DMA
– Secure Boot
– Physical (Enclosure) Protection
– 12 Tamper I/Os
– Wire Mesh
– Tamper Protection
– Voltage Monitoring
– Temperature Monitoring
– Crystal Monitoring
– Erasable Secure Memory for Encryption
Keys
– Configurable Tamper Response
– Tamper Events Log
– Partial ARM TrustZone With Secure Run-
Time Environment for Secure Applications
– On-the-Fly-Encryption (OTFE) of the DDR
Memory Bus Interface
– Touch Screen Controller, ADC0
1
– 12-Bit Successive Approximation Register
(SAR) ADC0
– Up to 867K Samples Per Second
– Input Can be Selected from Any of the Eight
Analog Inputs Multiplexed through an 8:1
Analog Switch
– Can Be Configured to Operate as a 4-, 5-, or
8-Wire Resistive Touch Screen Controller
(TSC) Interface
– Magnetic Card Reader, ADC1
– Up to Three 32-Bit Enhanced Capture (eCAP)
Modules
– Up to Three Enhanced Quadrature Encoder
Pulse (eQEP) Modules
– Up to Six Enhanced High-Resolution PWM
(eHRPWM) Modules
• MPU Subsystem
– ARM Cortex-A9 32-Bit RISC Microprocessor
With Processing Speed up to 1000 MHz
– 32KB of Both L1 Instruction and Data Cache
– 256KB of L2 Cache (Option to Configure as L3
RAM)
– 256KB of On-Chip Boot ROM
– 64KB of On-Chip RAM
– Secure Control Module (SCM)
– Emulation and Debug
– JTAG
– Embedded Trace Buffer
– Interrupt Controller
• On-Chip Memory (Shared L3 RAM)
– 256KB of General-Purpose On-Chip Memory
Controller (OCMC) RAM
– 8KB Erasable Memory
– Accessible to All Masters
– Supports Retention for Fast Wakeup
– Up to 512KB of Total Internal RAM
(256KB of ARM Memory Configured as L3 RAM
+ 256KB of OCMC RAM)
• External Memory Interfaces (EMIFs)
– DDR Controllers:
– LPDDR2: 266-MHz Clock (LPDDR2-533 Data
Rate)
– DDR3 and DDR3L: 400-MHz Clock (DDR-
800 Data Rate)
– 32-Bit Data Bus
– 2GB of Total Addressable Space
– Supports One x32, Two x16, or Four x8
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.