AM3359_12 Datasheet, PDF (1/197 Pages) Texas Instruments – AM335x ARM® Cortex™-A8 Microprocessors (MPUs)

AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com
SPRS717B – OCTOBER 2011 – REVISED JANUARY 2012
AM335x ARM^® Cortex™-A8 Microprocessors (MPUs)
Check for Samples: AM3359, AM3358
1 Device Summary
1.1 Features
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• Highlights
– 275-MHz, 500-MHz, 600-MHz, or 720-MHz
ARM^® Cortex™-A8 32-Bit RISC
Microprocessor
• NEON™ SIMD Coprocessor
• 32KB/32KB of L1 Instruction/Data Cache
with Single-Error Detection (parity)
• 256KB of L2 Cache with Error Correcting
Code (ECC)
– mDDR(LPDDR)/DDR2/DDR3 Support
– General-Purpose Memory Support (NAND,
NOR, SRAM, etc.) Supporting Up to 16-bit
ECC
– SGX530 Graphics Engine
– LCD Controller With WXGA Resolution at
60-Hz Refresh Rate
– Programmable Real-Time Unit Subsystem
– Real-Time Clock (RTC)
– Up to Two USB 2.0 High-Speed OTG Ports
with Integrated PHY
– 10/100/1000 Ethernet Switch Supporting Up
to Two Ports
– Serial Interfaces Including:
• Two Controller Area Network Ports (CAN)
• Six UARTs, Two McASPs, Two McSPI,
and Three I2C Ports
– 12-Bit Successive Approximation Register
(SAR) ADC
– Up to Three 32-Bit Enhanced Capture
Modules (eCAP)
– Up to Three Enhanced High-Resolution PWM
Modules (eHRPWM)
– Crypto Hardware Accelerators (AES, SHA,
PKA, RNG)
• MPU Subsystem
– 275-MHz, 500-MHz, 600-MHz, or 720-MHz
ARM^® Cortex™-A8 32-Bit RISC
Microprocessor
– NEON™ SIMD Coprocessor
– 32KB of L1 Instruction Cache with
Single-Error Detection (parity)
– 32KB of L1 Data Cache with Single
Error-Detection (parity)
– 256KB of L2 Cache with Error Correcting
Code (ECC)
– 176KB of On-Chip Boot ROM
– 64KB of Dedicated RAM
– Emulation/Debug
• JTAG
• Embedded Trace Buffer
– Interrupt Controller (up to 128 interrupt
requests)
• On-Chip Memory (Shared L3 RAM)
– 64 KB of General-Purpose On-Chip Memory
Controller (OCMC) RAM
– Accessible to all Masters
– Supports Retention for Fast Wake-Up
• External Memory Interfaces (EMIF)
– mDDR/DDR2/DDR3 Controller:
• mDDR: 200-MHz Clock (400-MHz Data
Rate)
• DDR2: 266-MHz Clock (532-MHz Data
Rate)
• DDR3: 303-MHz Clock (606-MHz Data
Rate)
• 16-Bit Data Bus
• 1 GB of Total Addressable Space
• Supports One x16 or Two x8 Memory
Device Configurations
• Supports Retention for Fast Wake-Up
– General-Purpose Memory Controller (GPMC)
• Flexible 8/16-Bit Asynchronous Memory
Interface with Up to seven Chip Selects
(NAND, NOR, Muxed-NOR, SRAM, etc.)
• Uses BCH Code to Support 4-Bit, 8-Bit, or
16-Bit ECC
• Uses Hamming Code to Support 1-Bit
ECC
1
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2
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3
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4
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6
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