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AFE5401-Q1_16 Datasheet, PDF (1/11 Pages) Texas Instruments – AFE5401-Q1 Quad-Channel, Analog Front-End for Automotive Radar Baseband Receiver
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AFE5401-Q1
SBAS636C – DECEMBER 2013 – REVISED MAY 2016
AFE5401-Q1 Quad-Channel, Analog Front-End for Automotive Radar Baseband Receiver
1 Features
•1 Integrated Analog Front-End Includes:
– Quad LNA, Equalizer, PGA, Antialiasing Filter,
and ADC
• PGA Input-Referred Noise: 3.0 nV/√Hz
• Simultaneous Sampling Across Channels
• Programmable LNA Gain
• Optional Equalizer Mode
• Programmable-Gain Amplifiers (PGAs)
• Programmable, Third-Order, Antialiasing Filter:
– 7 MHz, 8 MHz, 10.5 MHz, and 12 MHz
• Parallel CMOS Outputs
• 64-mW Total Core Power per Channel
• Supplies: 1.8 V and 3.3 V
3 Description
The AFE5401-Q1 includes four channels, with each
channel comprising a low-noise amplifier (LNA), an
optional equalizer (EQ), a programmable gain
amplifier (PGA), and an antialias filter followed by a
high-speed, 12-bit, analog-to-digital converter (ADC)
at 25 MSPS per channel.
The four ADC outputs are multiplexed on a 12-bit,
parallel, CMOS-compatible output bus.
To request a full data sheet or other design
resources: request AFE5401-Q1
Device Information
ORDER NUMBER
PACKAGE
BODY SIZE
AFE5401TRGCRQ1 VQFN (64)
9 mm × 9 mm
AFE5401TRGCTQ1 VQFN (64)
9 mm × 9 mm
2 Applications
• Automotive Radar
• Data Acquisition
• SONAR™
Functional Block Diagram
AVDD3
AVDD18
VCM
IN1
IN1_AUX
IN2
IN2_AUX
IN3
IN3_AUX
IN4
IN4_AUX
CLKINP
CLKINM
Reference
SERIAL
INTERFACE
LNA
PGA
EQ
AAF
EQ
BUF
EQ
EQ
BUF
EQ
EQ
BUF
EQ
EQ
BUF
CMOS/DIFF
SUPPORT
fCLKIN
AFE_CLK
Programmable
Clock Divider
ADC 1
ADC 2
ADC 3
4:1 MUX
ADC 4
1x
ADC_CLK
4x
Clock + Timing
Generator
DVDD18
DRVDD
D [11:0]
D_GPO [1:0]
DCLK
DSYNC1
DSYNC2
AVSS DVSS DRVSS
TRIG
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.