ADS808 Datasheet, PDF (1/24 Pages) Burr-Brown (TI) – 12-Bit, 70MHz Sampling ANALOG-TO-DIGITAL CONVERTER

ADS808
ADS808
SBAS179C – DECEMBER 2000 – REVISED SEPTEMBER 2002
12-Bit, 70MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q DYNAMIC RANGE:
SNR: 64dB at 10MHz f_IN
SFDR: 68dB at 10MHz f_IN
q PREMIUM TRACK-AND-HOLD:
Low Jitter: 0.25ps rms
Differential or Single-Ended Inputs
Selectable Full-Scale Input Range
q FLEXIBLE CLOCKING:
Differential or Single-Ended
Accepts Sine or Square Wave Clocking
Down to 0.5Vp-p
Variable Threshold Level
APPLICATIONS
q BASESTATION WIDEBAND RADIOS:
CDMA, GSM, TDMA, 3G, AMPS, and NMT
q TEST INSTRUMENTATION
q CCD IMAGING
DESCRIPTION
The ADS808 is a high-dynamic range, 12-bit, 70MHz,
pipelined Analog-to-Digital Converter (ADC). It includes a
high-bandwidth linear track-and-hold that has a low jitter of
only 0.25ps rms, leading to excellent SNR performance. The
clock input can accept a low-level differential sine wave or
square wave signal down to 0.5Vp-p, further improving the
SNR performance. It also accepts a single-ended clock
signal and has flexible threshold levels.
The ADS808 has a 2Vp-p differential input range (1Vp-p • 2
inputs) for optimum signal-to-noise ratio. The differential
operation gives the lowest even-order harmonic compo-
nents. A lower input voltage of 1.5Vp-p or 1Vp-p can also be
selected using the internal references, further optimizing
SFDR. Alternatively, a single-ended input range can be used
by tying the IN input to the common-mode voltage, if desired.
The ADS808 also provides an over-range flag that indicates
when the input signal has exceeded the converter’s full-scale
range. This flag can also be used to reduce the gain of the
front-end signal conditioning circuitry. It also employs digital
error-correction techniques to provide excellent differential
linearity for demanding imaging applications. The ADS808 is
available in a small TQFP-48 PowerPAD™ thermally en-
hanced package.
PowerPAD is a registered trademark of Texas Instruments.
1Vp-p
IN
1Vp-p
IN
ADS808
T&H
+V_S
DV
CLK
Timing Circuitry
CLK
12-Bit
Pipelined
ADC Core
Error
Correction
Logic
D0
3-State
Outputs
•••
D11
CM
(+2.5V)
Reference Ladder
and Driver
Reference and
Mode Select
OVR
REFT
V_REF SEL1 SEL2 REFB
OE VDRV
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 2000, Texas Instruments Incorporated