ADC32RF80 Datasheet, PDF (1/8 Pages) Texas Instruments – ADC32RF80 Dual-Channel

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ADC32RF80 Dual-Channel, 14-Bit, 3.0-GSPS,
RF Sampling Wideband Receiver and Feedback IC
ADC32RF80
SBAS774 – MAY 2016
1 Features
•1 Dual-Channel
• Maximum Clock Rate: 3.0-GSPS
• 14-Bit
• Noise Floor: –155 dBFS/Hz
• RF Input Supports Up to 4.0 GHz
• Aperture Jitter: 70 f_S
• Channel Isolation: 80 dB at f_IN = 1.8 GHz
• Spectral Performance (f_IN = 900 MHz):
– SNR: 60.6 dBFS
– SFDR: 65 dBc HD2, HD3
– SFDR: 75 dBFS Non HD2, HD3
• Spectral Performance (f_IN = 1.78 GHz):
– SNR: 58.0 dBFS
– SFDR: 63 dBc HD2, HD3
– SFDR: 72 dBFS Non HD2, HD3
• On-Chip Digital Down-Converters:
– Up to 4 DDCs (Dual-Band Mode)
– Up to 3 Independent NCOs per DDC
• On-Chip Input Clamp for Overvoltage Protection
• Programmable On-Chip Power Detectors with
Alarm Pins for AGC Support
• On-Chip Dither
• On-Chip, 50-Ω Input Termination
• Input Full-Scale: 1.35 V_PP
• Support for Multi-Chip Synchronization
• JESD204B Interface:
– Subclass 1-Based Deterministic Latency
– 4 Lanes Per ADC at 12.3 Gbps
• Power Supply:
– 1.9 V (Analog), 1.2 V (Analog), 1.15 V (Digital)
• Power Dissipation: 3.2 W/Ch at 3.0 GSPS
• 72-Pin VQFN Package (10 mm × 10 mm)
2 Applications
• Multi-Band, Multi-Mode 2G, 3G, 4G Cellular
Receivers
• Multi-Carrier Multi-Mode Cellular Infrastructure
Base Stations
• Telecommunications Receiver
• Telecom DPD Observation Receiver
3 Description
The ADC32RF80 is a 14-bit, 3.0-GSPS, dual-
channel, telecom receiver and feedback IC that
supports RF sampling with input frequencies up to
4 GHz and beyond. Designed for high signal-to-noise
ratio (SNR), the ADC32RF80 delivers a noise
spectral density of –155 dBFS/Hz as well as excellent
dynamic range and channel isolation over a large
input frequency range. The buffered analog input with
on-chip termination provides uniform input impedance
across a wide frequency range and minimizes
sample-and-hold glitch energy.
Each ADC channel is connected to a dual-band,
digital down-converter (DDC) with up to three
independent, 16-bit numerically-controlled oscillators
(NCOs) per DDC for phase-coherent frequency
hopping. Additionally, the ADC is equipped with front-
end peak and RMS power detectors and alarm
functions to support external automatic gain control
(AGC) algorithms.
The ADC32RF80 supports the JESD204B serial
interface with subclass 1-based deterministic latency
using data rates up to 12.3 Gbps with up to four lanes
per channel. The device is offered in a 72-pin VQFN
package (10 mm × 10 mm) and supports the
industrial temperature range (–40°C to +85°C).
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ADC32RF80
VQFN (72)
10.00 mm × 10.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
INAP/M
Buffer
50O
AAADADDCDCCC
GPIO1..4
FAST
DET.
CLKINP/M
SYSREFP/M
Buffer
INBP/M
50O
FAST
DET.
AAADADDCDCCC
Digital Block
Interleave
Correction
NCO
CTRL
N
N
NCO
NCO
PLL
DA[0,1]P/M
DA[2,3]P/M
SYNCBP/M
Digital Block
Interleave
Correction
NCO
NCO
N
N
DB[0,1]P/M
DB[2,3]P/M
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCT PREVIEW Information. Product in design phase of
development. Subject to change or discontinuance without notice.