ADC16DV160_14 Datasheet, PDF (1/36 Pages) Texas Instruments – Dual Channel, 16-Bit, 160 MSPS Analog-to-Digital Converter with DDR LVDS Outputs

ADC16DV160
www.ti.com
SNAS488G – AUGUST 2009 – REVISED AUGUST 2011
ADC16DV160 Dual Channel, 16-Bit, 160 MSPS Analog-to-Digital Converter with DDR LVDS
Outputs
Check for Samples: ADC16DV160
FEATURES
1
•2 Low power consumption
• On-chip precision reference and sample-and-
hold circuit
• On-chip automatic calibration during power-up
• Dual data rate LVDS output port
• Dual Supplies: 1.8V and 3.0V operation
• Selectable input range: 2.4 and 2.0 V_PP
• Sampling edge flipping with clock divider by 2
option
• Internal clock divide by 1 or 2
• On-chip low jitter duty-cycle stabilizer
• Power-down and sleep modes
• Output fixed pattern generation
• Output clock position adjustment
• 3-wire SPI
• Offset binary or 2's complement data format
• 68-pin LLP package (10x10x0.8, 0.5mm pin-
pitch)
APPLICATIONS
• Multi-carrier, Multi-standard Base Station
Receivers
– -MC-GSM/EDGE, CDMA2000, UMTS, LTE
and WiMAX
• High IF Sampling Receivers
• Diversity Channel Receivers
• Test and Measurement Equipment
• Communications Instrumentation
• Portable Instrumentation
DESCRIPTION
The ADC16DV160 is a monolithic dual channel high performance CMOS analog-to-digital converter capable of
converting analog input signals into 16-bit digital words at rates up to 160 Mega Samples Per Second (MSPS).
This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-
hold circuit to minimize power consumption and external component count while providing excellent dynamic
performance. Automatic power-up calibration enables excellent dynamic performance and reduces part-to-part
variation, and the ADC16DV160 can be re-calibrated at any time through the 3-wire Serial Peripheral Interface
(SPI). An integrated low noise and stable voltage reference and differential reference buffer amplifier eases
board level design. The on-chip duty cycle stabilizer with low additive jitter allows a wide range of input clock duty
cycles without compromising dynamic performance. A unique sample-and-hold stage yields a full-power
bandwidth of 1.4 GHz. The interface between the ADC16DV160 and a receiver block can be easily verified and
optimized via fixed pattern generation and output clock position features. The digital data is provided via dual
data rate LVDS outputs – making possible the 68-pin, 10 mm x 10 mm LLP package. The ADC16DV160
operates on dual power supplies of +1.8V and +3.0V with a power-down feature to reduce power consumption to
very low levels while allowing fast recovery to full operation.
1
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2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2011, Texas Instruments Incorporated