ADC12DL065_14 Datasheet, PDF (1/34 Pages) Texas Instruments – Dual 12-Bit, 65 MSPS, 3.3V, 360mW A/D Converter

ADC12DL065
www.ti.com
SNAS249C – MARCH 2005 – REVISED MAY 2005
ADC12DL065 Dual 12-Bit, 65 MSPS, 3.3V, 360mW A/D Converter
Check for Samples: ADC12DL065
FEATURES
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•23 Single +3.3V supply operation
• Internal sample-and-hold
• Internal reference
• Outputs 2.4V to 3.6V compatible
• Power down mode
• Duty Cycle Stabilizer
• Multiplexed Output Mode
APPLICATIONS
• Ultrasound and Imaging
• Instrumentation
• Communications Receivers
• Sonar/Radar
• xDSL
• Cable Modems
• DSP Front Ends
DESCRIPTION
The ADC12DL065 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting
analog input signals into 12-bit digital words at 65 Megasamples per second (MSPS). This converter uses a
differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize
power consumption while providing excellent dynamic performance and a 250 MHz Full Power Bandwidth.
Operating on a single +3.3V power supply, the ADC12DL065 achieves 11.0 effective bits at nyquist and
consumes just 360 mW at 65 MSPS, including the reference current. The Power Down feature reduces power
consumption to 36 mW.
The differential inputs provide a full scale differential input swing equal to 2 times V_REF with the possibility of a
single-ended input. Full use of the differential input is recommended for optimum performance. The digital
outputs from the two ADC's are available on a single multiplexed 12-bit bus or on separate buses. Duty cycle
stabilization and output data format are selectable using a quad state function pin. The output data can be set for
offset binary or two's complement.
To ease interfacing to lower voltage systems, the digital output driver power pins of the ADC12DL065 can be
connected to a separate supply voltage in the range of 2.4V to the analog supply voltage. This device is available
in the 64-lead TQFP package and will operate over the industrial temperature range of −40°C to +85°C. An
evaluation board is available to ease the evaluation process.
Resolution
DNL
SNR (f_IN = 10 MHz)
SFDR (f_IN = 10 MHz)
Data Latency
Power Consumption
● Operating
● Power Down Mode
Table 1. Key Specifications
VALUE
12
±0.4
69
86
7
360
36
UNIT
Bits
LSB (typ)
dB (typ)
dB (typ)
Clock Cycles
mW (typ)
mW (typ)
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TRI-STATE is a registered trademark of National Semiconductor Corporation.
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All other trademarks are the property of their respective owners.
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated