74SSTUB32865 Datasheet, PDF (1/21 Pages) Texas Instruments – 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

74SSTUB32865
www.ti.com
SLAS537 – NOVEMBER 2007
28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST
FEATURES
1
•2 Member of the Texas Instruments Widebus+™
Family
• Pinout Optimizes DDR2 RDIMM PCB Layout
• 1-to-2 Outputs Supports Stacked DDR2
RDIMMs
• Chip-Select Inputs Gate the Data Outputs from
Changing State and Minimizes System Power
Consumption
• Output Edge-Control Circuitry Minimizes
Switching Noise in an Unterminated Line
• Supports SSTL_18 Data Inputs
• Differential Clock (CK and CK) Inputs
• Supports LVCMOS Switching Levels on the
Chip-Select Gate-Enable and RESET Inputs
• Checks Parity on DIMM-Independent Data
Inputs
• Industrial Temperature range for T_A -40°C to
85°C supported
• RESET Input Disables Differential Input
Receivers, Resets All Registers, and Forces
All Outputs Low, Except PTYERR
DESCRIPTION
This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V V_CC operation. One device per DIMM
is required to drive up to 18 SDRAM loads or two devices per DIMM are required to drive up to 36 SDRAM
loads.
All inputs are SSTL_18, except the chip-select gate-enable (CSGateEN) and reset (RESET) inputs, which are
LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18
specifications, except the open-drain error (PTYERR) output.
The 74SSTUB32865 operates from a differential clock (CK and CK). Data are registered at the crossing of CK
going high and CK going low.
The 74SSTUB32865 accepts a parity bit from the memory controller on the parity bit (PARIN) input, compares it
with the data received on the DIMM-independent D-inputs (D0-D21) and indicates whether a parity error has
occurred on the open-drain PTYERR pin (active low). The convention is even parity, i.e., valid parity is defined as
an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To
calculate parity, all DIMM-independent D-inputs must be tied to a known logic state.
ORDERING INFORMATION
T_A
-40°C to 85°C
PACKAGE ⁽¹⁾
TFBGA-ZJB
Tape and reel
ORDERABLE
PART NUMBER
74SSTUB32865ZJBR
TOP-SIDE
MARKING
SB865
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated