74ACT16821 Datasheet, PDF (1/9 Pages) Texas Instruments – 20-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

54ACT16821, 74ACT16821
20ĆBIT BUSĆINTERFACE FLIPĆFLOPS
WITH 3ĆSTATE OUTPUTS
SCAS176A − JANUARY 1991 − REVISED APRIL 1996
D Members of the Texas Instruments
Widebus Family
D Inputs Are TTL-Voltage Compatible
D Provide Extra Data Width Necessary for
Wider Address/Data Paths or Buses With
Parity
D Flow-Through Architecture Optimizes
PCB Layout
D Distributed V_CC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
D Package Options Include 300-mil Shrink
Small-Outline (DL) Packages Using 25-mil
Center-to-Center Pin Spacings and 380-mil
Fine-Pitch Ceramic Flat (WD) Packages
Using 25-mil Center-to-Center Pin Spacings
description
These 20-bit flip-flops feature 3-state outputs
designed specifically for driving highly-capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, parity bus interfacing, and
working registers.
The ’ACT16821 can be used as two 10-bit
flip-flops or one 20-bit flip-flop. On the positive
transition of the clock (CLK) input, the Q outputs
follow the data (D) inputs. Each 10-bit flip-flop
section has a buffered output-enable (1OE or
2OE) input that can be used to place the ten
outputs in either a normal logic state (high or low
logic levels) or the high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly.
54ACT16821 . . . WD PACKAGE
74ACT16821 . . . DL PACKAGE
(TOP VIEW)
1OE 1
1Q1 2
1Q2 3
GND 4
1Q3 5
1Q4 6
V_CC 7
1Q5 8
1Q6 9
1Q7 10
GND 11
1Q8 12
1Q9 13
1Q10 14
2Q1 15
2Q2 16
2Q3 17
GND 18
2Q4 19
2Q5 20
2Q6 21
V_CC 22
2Q7 23
2Q8 24
GND 25
2Q9 26
2Q10 27
2OE 28
56 1CLK
55 1D1
54 1D2
53 GND
52 1D3
51 1D4
50 V_CC
49 1D5
48 1D6
47 1D7
46 GND
45 1D8
44 1D9
43 1D10
42 2D1
41 2D2
40 2D3
39 GND
38 2D4
37 2D5
36 2D6
35 V_CC
34 2D7
33 2D8
32 GND
31 2D9
30 2D10
29 2CLK
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The 74ACT16821 is packaged in theTI shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16821 is characterized for operation over the full military temperature range of −55°C to 125°C. The
74ACT16821 is characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
Copyright  1996, Texas Instruments Incorporated
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