74ACT11478 Datasheet, PDF (1/5 Pages) Texas Instruments – METASTABLE-RESISTAND OCTAL D-TYPE DUAL-RANK FLIP-FLOP WITH 3-STATE OUTPUTS

74ACT11478
METASTABLEĆRESISTAND OCTAL DĆTYPE DUALĆRANK FLIPĆFLOP
WITH 3-STATE OUTPUTS
SCAS131 − APRIL 1990 − REVISED APRIL 1993
• Inputs Are TTL-Voltage Compatible
• Specifically Designed for Data
Synchronization Applications
• Improved Metastable Characteristics
Provide Greater System Reliability
• 3-State Outputs Drive Bus Lines Directly
• Flow-Through Architecture to Optimize
PCB Layout
• Center-Pin V_CC and GND Configurations to
Minimize High-Speed Switching Noise
• EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
• 500-mA Typical Latch-Up Immunity
at 125°C
• Package Options Include Plastic Small
Outline Packages and Standard Plastic
300-mil DIPs
DW OR NT PACKAGE
(TOP VIEW)
1Q 1
2Q 2
3Q 3
4Q 4
GND 5
GND 6
GND 7
GND ⁸
5Q ⁹
6Q ¹⁰
7Q ¹¹
8Q ¹²
24 OE
23 1D
22 2D
21 3D
20 4D
19 V_CC
18 V_CC
17 _5D
16 _6D
15 _7D
14 _8D
13 _CLK
description
The 74ACT11478 is an 8-bit dual-rank synchronizer circuit designed specifically for data synchronization
applications where the normal setup and hold time specifications are frequently violated.
Synchronization of two digital signals operating at different frequencies is a common system problem. This
problem is typically solved by synchronizing one of the signals to the local clock through a flip-flop. This solution,
however, causes the setup and hold time specifications associated with the flip-flop to be violated. When the
setup or hold time specification is violated, the output response is uncertain.
A flip-flop is metastable if its output hangs up in the region between V_IL and V_IH. The metastable condition lasts
until the flip-flop recovers into one of its two stable states. With conventional flip-flops, this recovery time can
be longer than the specified maximum propagation delay.
The problem of metastability is typically solved by adding an additional layer of synchronization. This type of
dual ranking is employed in the 74ACT11478. The probability of the second stage entering the metastable state
is exponentially reduced by this dual-rank architecture. The 74ACT11478 provides a one-chip solution for
system designers in asynchronous applications.
The 74ACT11478 is characterized for operation from − 40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE CLOCK† D
OUTPUT
Q
H
X
X
Z
L
↑
L
L
L
↑
H
H
L
H
X
QO
† _{Data presented at the D input requires two}
clock cycles to appear at the Q output.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1993, Texas Instruments Incorporated
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