74ACT11181 Datasheet, PDF (1/14 Pages) Texas Instruments – ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR

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74ACT11181
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
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SCAS086 − D3200, OCTOBER 1989 − REVISED APRIL 1993
• Inputs Are TTL-Voltage Compatible
• New Flow-Through Architecture Optimizes
PCB Layout
• Center-Pin V_CC and GND Configurations
Minimize High-Speed Switching Noise
• EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Full Look Ahead for High-Speed Operations
on Long Words
• Arithmetic Operating Modes:
Addition
Subtraction
Shift Operand A One Position
Magnitude Comparison
Plus Twelve Other Arithmetic
Operations
• Logic Function Modes:
Exclusive-OR
Comparator
AND, NAND, OR, NOR
DW PACKAGE
(TOP VIEW)
C_n 1
M2
A=B 3
F0 4
F1 5
GND 6
GND 7
GND 8
GND 9
F2 10
F3 11
P ¹²
G ¹³
C_{n + 4} ¹⁴
28 A0
27 A1
26 A2
25 A3
24 B0
23 B1
22 V_CC
21 V_CC
20 B2
19 B3
18 S0
17 _S1
16 _S2
15 _S3
logic symbol^†
18
S0
17
S1
16
S2
15
S3
2
M
Cn ¹
28
A0
24
B0
27
A1
23
B1
26
A2
20
B2
25
A3
19
B3
ALU
0
0
M ₃₁
4
CI
(0 ... 15) CP
(0 ... 15) CG
6(P = Q)
(0 ... 15) CO
P
[1]
Q
P
[2]
Q
P
[4]
Q
P
[8]
Q
† _{This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.}
12
P
13
G
3
A=B
14
Cn+4
4 _F0
5 _F1
10
F2
11
F3
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  1993, Texas Instruments Incorporated
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