74AC11109_09 Datasheet, PDF (1/7 Pages) Texas Instruments – DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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54AC11109, 74AC11109
DUAL JĆK POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS
WITH CLEAR AND PRESET
SCAS450 − MARCH 1987 − REVISED APRIL 1993
• Flow-Through Architecture Optimizes
PCB Layout
• Center-Pin V_CC and GND Configurations
Minimize High-Speed Switching Noise
• EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
• 500-mA Typical Latch-Up Immunity
at 125°C
• ESD Protection Exceeds 2000 V,
MIL STD-883C Method 3015
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
54AC11109 . . . J PACKAGE
74AC11109 . . . D OR N PACKAGE
(TOP VIEW)
1PRE ₁
1Q 2
1Q 3
GND 4
2Q 5
2Q 6
2PRE 7
2CLK 8
16 ^1CLK
15 1K
14 1J
13 1CLR
12 V_CC
11 2CLR
10 2J
9 2K
54AC11109 . . . FK PACKAGE
(TOP VIEW)
description
These devices contain two independent J-K
positive-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs regardless of the levels of the
other inputs. When preset and clear are inactive
(high), data at the J and K inputs meeting the setup
time requirements are transferred to the outputs
on the positive-going edge of the clock pulse.
Clock triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse.
Following the hold time interval, data at the J and
K inputs may be changed without affecting the
levels at the outputs. These versatile flip-flops can
perform as toggle flip-flops by grounding K and
tying J high. They also can perform as D-type
flip-flops by tying the J and K inputs together.
1K
1CLK
NC
1PRE
1Q
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2J
2K
NC
2CLK
2PRE
NC − No internal connection
The 54AC11109 is characterized for operation over the full military temperature range of −55°C to 125°C. The
74AC11109 is characterized for operation from − 40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUTS
PRE CLR CLK J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H†
H†
H
H
↑
L
L
L
H
H
H
↑
H
L
Toggle
H
H
↑
L
H
Q0 Q0
H
H
↑
H
H
H
L
H
H
L
X
X
Q0 Q0
† _{This configuration is nonstable; that is, it will not persist when}
either PRE or CLR returns to its inactive (high) level.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1993, Texas Instruments Incorporated
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