54ACT16657_08 Datasheet, PDF (1/11 Pages) Texas Instruments – 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS

54ACT16657, 74ACT16657
16-BIT TRANSCEIVERS
WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SCAS164A – JANUARY 1991 – REVISED APRIL 1996
D Members of the Texas Instruments
Widebus™ Family
D Inputs Are TTL-Voltage Compatible
D Flow-Through Architecture Optimizes
PCB Layout
D Distributed V_CC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D EPIC™ (Enhanced-Performance Implanted
CMOS) 1-µm Process
D 500-mA Typical Latch-Up Immunity at
125°C
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The ’ACT16657 contain two noninverting octal
transceiver sections with separate parity
generator/checker circuits and control signals.
For either section, the transmit/receive (1T/R or
2T/R) input determines the direction of data flow.
When 1T/R (or 2T/R) is high, data flows from the
1A (or 2A) port to the 1B (or 2B) port (transmit
mode); when 1T/R (or 2T/R) is low, data flows
from the 1B (or 2B) port to the 1A (or 2A) port
(receive mode). When the output-enable (1OE or
2OE) input is high, both the 1A (or 2A) and 1B (or
2B) ports are in the high-impedance state.
54ACT16657 . . . WD PACKAGE
74ACT16657 . . . DL PACKAGE
(TOP VIEW)
1OE 1
NC 2
1ERR 3
GND 4
1A1 5
1A2 6
V_CC 7
1A3 8
1A4 9
1A5 10
GND 11
1A6 12
1A7 13
1A8 14
2A1 15
2A2 16
2A3 17
GND 18
2A4 19
2A5 20
2A6 21
V_CC ²²
2A7 ²³
2A8 ²⁴
GND ²⁵
2ERR ²⁶
NC ²⁷
2OE ²⁸
56 ^1T/R
55 ^1ODD/EVEN
54 ^1PARITY
53 ^GND
52 ^1B1
51 ^1B2
50 ^VCC
49 ^1B3
48 ^1B4
47 ^1B5
46 ^GND
45 ^1B6
44 ^1B7
43 ^1B8
42 ^2B1
41 ^2B2
40 ^2B3
39 GND
38 2B4
37 2B5
36 2B6
35 V_CC
34 2B7
33 2B8
32 GND
31 2PARITY
30 2ODD/EVEN
29 2T/R
Odd or even parity is selected by a logic high or
low level, respectively, on the 1ODD/EVEN (or
2ODD/EVEN) input. 1PARITY (or 2PARITY)
carries the parity bit value; it is an output from the
parity generator/checker in the transmit mode and
an input to the parity generator/checker in the
receive mode.
NC – No internal connection
In the transmit mode, after the 1A (or 2A) bus is polled to determine the number of high bits, 1PARITY (or
2PARITY) is set to the logic level that maintains the parity sense selected by the level at the 1ODD/EVEN (or
2ODD/EVEN) input. For example, if 1ODD/EVEN is low (even parity selected) and there are five high bits on
the 1A bus, then 1PARITY is set to the logic high level so that an even number of the nine total bits (eight 1A-bus
bits plus parity bit) are high.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1996, Texas Instruments Incorporated
1