54ACT11011_09 Datasheet, PDF (1/5 Pages) Texas Instruments – TRIPLE 3-INPUT POSITIVE-AND GATES

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• Inputs Are TTL-Voltage Compatible
• Flow-Through Architecture Optimizes
PCB Layout
• Center-Pin V_CC and GND Configurations
Minimize High-Speed Switching Noise
• EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
• 500-mA Typical Latch-Up Immunity
at 125°C
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
These devices contain three independent 3-input
AND gates. They perform the Boolean functions
Y = ASBSC or Y = A + B + C in positive logic.
The 54ACT11011 is characterized for operation
over the full military temperature range of − 55°C
to 125°C. The 74ACT11011 is characterized for
operation from − 40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
A
B
C
OUTPUT
Y
H
H
H
H
L
X
X
L
X
L
X
L
X
X
L
L
logic symbol^†
1
1A
&
16
1B
15
1C
14
2A
11
2B
10
2C
9
3A
8
3B
7
3C
2
1Y
3
2Y
6
3Y
† _{This symbol is in accordance with ANSI/IEEE Std 91-1984}
and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
54ACT11011, 74ACT11011
TRIPLE 3ĆINPUT POSITIVEĆAND GATES
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SCAS028A − D2957, JULY 1987 − REVISED APRIL 1993
54ACT11011 . . . J PACKAGE
74ACT11011 . . . D OR N PACKAGE
(TOP VIEW)
1A 1
1Y 2
2Y 3
GND 4
GND ⁵
3Y ⁶
3C ⁷
3B ⁸
16 1B
15 1C
14 2A
13 V_CC
12 _VCC
11 _2B
10 _2C
9 _3A
54ACT11011 . . . FK PACKAGE
(TOP VIEW)
1C
3 2 1 20 19
4
18
2C
1B ₅
17 ^3A
NC 6
16 NC
1A 7
15 3B
1Y 8
14 3C
9 10 11 12 13
NC − No internal connection
logic diagram (positive logic)
1A
1B
1Y
1C
2A
2B
2Y
2C
3A
3B
3Y
3C
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1993, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
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