100355 Datasheet, PDF (1/9 Pages) National Semiconductor (TI) – Low Power Quad Multiplexer/Latch

OBSOLETE
100355
www.ti.com
SNOS110B – AUGUST 1998 – REVISED APRIL 2013
100355 Low Power Quad Multiplexer/Latch
Check for Samples: 100355
FEATURES
1
•2 Greater than 40% Power Reduction of the
100155
• 2000V ESD Protection
• Pin/Function Compatible with 100155
• Voltage Compensated Operating Range =
−4.2V to −5.7V
• Standard Microcircuit Drawing
– (SMD) 5962-9165401
DESCRIPTION
The 100355 contains four transparent latches, each
of which can accept and store data from two sources.
When both Enable (E_n) inputs are LOW, the data that
appears at an output is controlled by the Select (S_n)
inputs, as shown in the Operating Mode table. In
addition to routing data from either D₀ or D₁, the
Select inputs can force the outputs LOW for the case
where the latch is transparent (both Enables are
LOW) and can steer a HIGH signal from either D₀ or
D₁ to an output. The Select inputs can be tied
together for applications requiring only that data be
steered from either D₀ or D₁. A positive-going signal
on either Enable input latches the outputs. A HIGH
signal on the Master Reset (MR) input overrides all
the other inputs and forces the Q outputs LOW. All
inputs have 50 kΩ pulldown resistors.
E₁, E₂
S₀, S₁
MR
D_na–D_nd
Q_a–Q_d
Q_a–Q_d
Pin Names
Table 1. PIN DESCRIPTION
Enable Inputs (Active LOW)
Select Inputs
Master Reset
Data Inputs
Data Outputs
Complementary Data Outputs
Description
1
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2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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