TLV320AIC3254 Datasheet, PDF (92/168 Pages) Texas Instruments – Ultra Low Power Stereo Audio Codec With Embedded miniDSP

TLV320AIC3254
Ultra Low Power Stereo Audio Codec With Embedded miniDSP
SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008
www.ti.com
5.18.2.1 I²C CONTROL MODE
The TLV320AIC3254 supports the I²C control protocol, and will respond to the I²C address of 0011000.
I²C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices
on the I²C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines
HIGH. Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no
device is driving them LOW. This way, two devices cannot conflict; if two devices drive the bus
simultaneously, there is no driver contention.
Communication on the I²C bus always takes place between two devices, one acting as the master and the
other acting as the slave. Both masters and slaves can read and write, but slaves can only do so under
the direction of the master. Some I²C devices can act as masters or slaves, but the TLV320AIC3254 can
only act as a slave device.
An I²C bus consists of two lines, SDA and SCL. SDA carries data, and the SCL signal provides the clock.
All data is transmitted across the I²C bus in groups of eight bits. To send a bit on the I²C bus, the SDA line
is driven to the appropriate level while SCL is LOW (a LOW on SDA indicates the bit is zero, while a HIGH
indicates the bit is one).
Once the SDA line has settled, the SCL line is brought HIGH, then LOW. This pulse on the SCL line
clocks the SDA bit into the receiver’s shift register.
The I²C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master
reads from a slave, the slave drives the data line; when a master sends to a slave, the master drives the
data line.
Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When
communication is taking place, the bus is active. Only master devices can start communication on the bus.
Normally, the data line is only allowed to change state while the clock line is LOW. If the data line changes
state while the clock line is HIGH, it is either a START condition or its counterpart, a STOP condition. A
START condition is when the clock line is HIGH and the data line goes from HIGH to LOW. A STOP
condition is when the clock line is HIGH and the data line goes from LOW to HIGH.
After the master issues a START condition, it sends a byte that selects the slave device for
communication. This byte is called the address byte. Each device on an I²C bus has a unique 7-bit
address to which it responds. (Slaves can also have 10-bit addresses; see the I²C specification for
details.) The master sends an address in the address byte, together with a bit that indicates whether it
wishes to read from or write to the slave device.
Every byte transmitted on the I²C bus, whether it is address or data, is acknowledged with an
acknowledge bit. When a master has finished sending a byte (eight data bits) to a slave, it stops driving
SDA and waits for the slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA
LOW. The master then sends a clock pulse to clock the acknowledge bit. Similarly, when a master has
finished reading a byte, it pulls SDA LOW to acknowledge this to the slave. It then sends a clock pulse to
clock the bit. (Remember that the master always drives the clock line.)
A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is
not present on the bus, and the master attempts to address it, it will receive a not–acknowledge because
no device is present at that address to pull the line LOW.
When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP
condition is issued, the bus becomes idle again. A master may also issue another START condition. When
a START condition is issued while the bus is active, it is called a repeated START condition.
The TLV320AIC3254 can also respond to and acknowledge a General Call, which consists of the master
issuing a command with a slave address byte of 00H. This feature is disabled by default, but can be
enabled via Page 0, Register 34, Bit D(5).
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